公开(公告)号：US09659959B2

公开(公告)日：2017-05-23

申请号：US15334968

申请日：2016-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Duk Lee ,  Young-Woo Park

IPC: H01L21/336 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11568 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/02 ,  H01L21/28 ,  H01L23/528

CPC classification number: H01L21/02636 ,  H01L21/28282 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.

公开(公告)号：US08951881B2

公开(公告)日：2015-02-10

申请号：US14279786

申请日：2014-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Lee ,  Jang-Hyun You ,  Jee-Hoon Han ,  Young-Woo Park ,  Sung-Hoi Hur ,  Sang-Ick Joo

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L21/76224 ,  H01L21/76229 ,  H01L21/764

Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.

Abstract translation: 制造非易失性存储器件的方法包括在衬底中形成限定器件隔离区域的衬底中的沟槽，并且其间的有源区域。 沟槽和其间的有源区延伸到衬底的第一和第二器件区域。 牺牲层形成在第一器件区域中的有源区之间的沟槽中，并且形成绝缘层以基本上填充第二器件区域中的有源区之间的沟槽。 选择性地去除第一器件区域中的沟槽中的牺牲层的至少一部分，以限定沿着第一器件区域中的有源区之间的沟槽延伸的间隙区域，同时基本上将沟槽中的绝缘层保持在有源区 在第二设备区域中。 还讨论了相关的方法和设备。

公开(公告)号：US09899408B2

公开(公告)日：2018-02-20

申请号：US15189205

申请日：2016-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hwan Son ,  Young-Woo Park ,  Jae-Duk Lee

IPC: H01L27/11582 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: A non-volatile memory device having a vertical structure includes: a first interlayer insulating layer on a substrate; a first gate electrode disposed on the first interlayer insulating layer; second interlayer insulating layers and second gate electrodes alternately stacked on the first gate electrode; an opening portion penetrating the first gate electrode, the second interlayer insulating layers, and the second gate electrodes and exposing the first interlayer insulating layer; a gate dielectric layer covering side walls and a bottom surface of the opening portion; and a channel region formed on the gate dielectric layer, and penetrating a bottom surface of the gate dielectric layer and the first interlayer insulating layer and thus electrically connected to the substrate, wherein a separation distance between side walls of the gate dielectric layer in a region which contacts the first gate electrode is greater than that in a region which contacts any one of the second gate electrodes.

公开(公告)号：USRE45592E1

公开(公告)日：2015-06-30

申请号：US14487817

申请日：2014-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Woo Park

IPC: G02B13/22 ,  G02B13/18 ,  G02B9/34 ,  G02B15/173 ,  G02B13/16 ,  G02B13/00 ,  G02B27/28

CPC classification number: G02B9/34 ,  G02B13/004 ,  G02B13/16 ,  G02B13/18 ,  G02B13/22 ,  G02B15/173 ,  G02B27/286

Abstract: The present invention is directed to a photographing lens containing, in order from an object side: a first lens having a positive refractive power and a convex surface facing the object side; a second lens having a negative refractive power; a third lens having a positive refractive power; and a fourth lens having a negative refractive power and at least one aspheric surface, the photographing lens satisfying the following conditional expressions: L T f ≤ 1.2 0.5 ≤ f 3 f ≤ 1.0 where LT denotes the distance on the optical axis between the object side of the first lens and the image side of the fourth lens; f denotes the total focal length of the photographing lens; and f3 denotes the focal length of the third lens.

Abstract translation: 本发明涉及一种摄影镜头，其从物体侧依次包括具有正折光力的第一透镜和面向物体侧的凸面; 具有负屈光力的第二透镜; 具有正屈光力的第三透镜; 以及具有负屈光力和至少一个非球面的第四透镜，所述拍摄透镜满足以下条件表达式：LTf≤1.20.5≤f3 f≤1.0其中，LT表示在光轴的物体侧之间的距离 第一透镜和第四透镜的像侧; f表示拍摄镜头的总焦距; f3表示第三透镜的焦距。

公开(公告)号：US20240268110A1

公开(公告)日：2024-08-08

申请号：US18640528

申请日：2024-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoo-Cheol Shin ,  Young-Woo Park ,  Jae-Duk Lee

IPC: H10B43/20 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H10B41/20 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B43/20 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/20 ,  H10B41/27 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.

公开(公告)号：US09634024B2

公开(公告)日：2017-04-25

申请号：US14642086

申请日：2015-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji Kanamori ,  Chung-Jin Kim ,  Young-Woo Park ,  Jae-Goo Lee ,  Jae-Duk Lee ,  Moo-Rym Choi

IPC: H01L29/792 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor device is provided. Word lines are formed on a substrate. An air gap is interposed between two adjacent word lines. A channel structure penetrates through the word lines and the air gap. A memory cell is interposed between each word line and the channel structure. The memory cell includes a blocking pattern, a charge trap pattern and a tunneling insulating pattern. The blocking pattern conformally covers a top surface, a bottom surface, and a first side surface of each word line. The first side surface is adjacent to the channel structure. The charge trap pattern is interposed only between the first side surface and the channel structure.

公开(公告)号：US12293977B2

公开(公告)日：2025-05-06

申请号：US18429039

申请日：2024-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Woo Park

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/053 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

Abstract: A method of fabricating a semiconductor package includes mounting at least one semiconductor chip to a package substrate, forming a shielding wall around the at least one semiconductor chip, forming a molded body on the package substrate in a space surrounded by the shielding wall, and forming a shielding cover covering the molding unit and in contact with the shielding wall.

公开(公告)号：US20240213177A1

公开(公告)日：2024-06-27

申请号：US18429039

申请日：2024-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Woo Park

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/053 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/552 ,  H01L21/4817 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/053 ,  H01L23/3128 ,  H01L23/49838 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/48157 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/3025

Abstract: A method of fabricating a semiconductor package includes mounting at least one semiconductor chip to a package substrate, forming a shielding wall around the at least one semiconductor chip, forming a molded body on the package substrate in a space surrounded by the shielding wall, and forming a shielding cover covering the molding unit and in contact with the shielding wall.

公开(公告)号：US10943872B2

公开(公告)日：2021-03-09

申请号：US16224556

申请日：2018-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Woo Park

IPC: H01L23/552 ,  H01L25/10 ,  H01L25/065 ,  H01L23/00 ,  H01L23/053 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A method of fabricating a semiconductor package includes mounting at least one semiconductor chip to a package substrate, forming a shielding wall around the at least one semiconductor chip, forming a molded body on the package substrate in a space surrounded by the shielding wall, and forming a shielding cover covering the molding unit and in contact with the shielding wall.

公开(公告)号：US10026611B2

公开(公告)日：2018-07-17

申请号：US15590926

申请日：2017-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Duk Lee ,  Young-Woo Park

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11568 ,  H01L23/528 ,  H01L27/11565

Abstract: A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.