公开(公告)号：US20240244843A1

公开(公告)日：2024-07-18

申请号：US18618451

申请日：2024-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hyun CHO ,  Kwang Ho LEE ,  Ji Hwan YU ,  Jong Soo KIM

IPC: H10B43/27 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H10B43/10 ,  H10B43/35

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.

公开(公告)号：US20190027491A1

公开(公告)日：2019-01-24

申请号：US15937932

申请日：2018-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： KWANG HO LEE ,  Kwang Ho KIM ,  Seung Hynu CHO ,  Ji Hwan YU

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L23/528 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/11573

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.

公开(公告)号：US20210313352A1

公开(公告)日：2021-10-07

申请号：US17354516

申请日：2021-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hyun CHO ,  Kwang Ho LEE ,  Ji Hwan YU ,  Jong Soo KIM

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is firmed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.

公开(公告)号：US20200303412A1

公开(公告)日：2020-09-24

申请号：US16890400

申请日：2020-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hyun CHO ,  Kwang Ho LEE ,  Ji Hwan YU ,  Jong Soo KIM

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11565

Abstract: A semiconductor device includes a plurality of blocks on a substrate. Trenches are disposed between the plurality of blocks. Conductive patterns are formed inside the trenches. A lower end of an outermost trench among the trenches is formed at a level higher than a level of a lower end of the trench adjacent to the outermost trench. Each of the blocks includes insulating layers and gate electrodes, which are alternately and repeatedly stacked. Pillars pass through the insulating layers and the gate electrodes along a direction orthogonal to an upper surface of the substrate.