公开(公告)号：US20190027491A1

公开(公告)日：2019-01-24

申请号：US15937932

申请日：2018-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： KWANG HO LEE ,  Kwang Ho KIM ,  Seung Hynu CHO ,  Ji Hwan YU

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L23/528 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/11573

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.

公开(公告)号：US20190214407A1

公开(公告)日：2019-07-11

申请号：US16358182

申请日：2019-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： KWANG HO LEE ,  Kwang Ho Kim ,  Seung-Hyun Cho ,  Ji Hwan Yu

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L29/423 ,  H01L27/11573 ,  H01L23/528 ,  H01L27/11575 ,  H01L27/1157 ,  H01L27/11568

CPC classification number: H01L27/11582 ,  H01L23/528 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/1037 ,  H01L29/4234 ,  H01L29/7889

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region of the substrate, and forming a stepped structure in the connection region, a first metal line dividing the plurality of gate electrode layers and connected to the cell array region and the connection region of the substrate, and a second metal line dividing a portion of the plurality of gate electrode layers and connected to the connection region of the substrate. A depth of a lower end portion of the second metal line may be greater than a depth of a lower end portion of the first metal line in the cell array region, based on an upper surface of the substrate.