公开(公告)号：US20240265977A1

公开(公告)日：2024-08-08

申请号：US18366368

申请日：2023-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryul KIM ,  Yongsung CHO

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/24

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/24

Abstract: A flash memory device including a cell string including memory cells, a page buffer connected to the cell string and a bit line and configured to sense data stored in a selected memory cell by pre-charging a sensing node connected to the bit line, the page buffer including a latch including a latch node and an inverted latch node, a sampling switch circuit configured to perform a trip voltage sampling operation by electrically connecting the latch node and the sensing node according to a sampling control signal, and a pull-down NMOS transistor configured to define a trip voltage provided to the latch node based on a sensing result of the data stored in the selected memory cell, and a voltage regulator configured to adjust the trip voltage by providing a source voltage to the pull-down NMOS transistor of the page buffer, may be provided.

公开(公告)号：US20210090651A1

公开(公告)日：2021-03-25

申请号：US16999189

申请日：2020-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongryul KIM ,  Jinyoung KIM ,  Taehui NA

IPC: G11C13/00 ,  G11C11/56

Abstract: A memory device and a method of operating the same. The memory device includes a memory cell array including a plurality of memory cells disposed in an area where a plurality of word lines and a plurality of bit lines cross each other; a row decoder including row switches and configured to perform a selection operation on the plurality of word lines; a column decoder including column switches and configured to perform a selection operation on the plurality of bit lines; and a control logic configured to control, in a data read operation, a precharge operation to be performed on a selected word line in a word line precharge period, and to control a precharge operation to be performed on a selected bit line in a bit line precharge period; wherein a row switch connected to the selected word line is weakly turned on in the bit line precharge period.