公开(公告)号：US20210091086A1

公开(公告)日：2021-03-25

申请号：US17112195

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Augustin Jinwoo HONG ,  Young-Ju LEE ,  Joon-Yong CHOE ,  Jung-hyun KIM ,  Sang-jun LEE ,  Hyeon-Kyu LEE ,  Yoon-Chul CHO ,  Je-Min PARK ,  Hyo-Dong BAN

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/535

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

公开(公告)号：US20180350818A1

公开(公告)日：2018-12-06

申请号：US15884504

申请日：2018-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-sic YOON ,  Ki-seok LEE ,  Jung-hyun KIM ,  Je-min PARK

IPC: H01L27/108

CPC classification number: H01L27/10888 ,  H01L21/02697 ,  H01L21/768 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor device includes first wiring line patterns on a support layer, second wiring line patterns on the first wiring line patterns, and a multiple insulation pattern. The first wiring line patterns extend in a first direction and are spaced apart from each other in a second direction. The support layer includes first contact hole patterns between the first wiring line patterns that are spaced apart from each other in the first and second directions. The second wiring line patterns extend in the second direction perpendicular and are spaced apart from each other in the first direction. The multiple insulation pattern is on an upper surface of the support layer where the first contact hole patterns are not formed, arranged in a third direction perpendicular to the first direction and the second direction, and between the first wiring line patterns and the second wiring line patterns.