公开(公告)号：US20200091305A1

公开(公告)日：2020-03-19

申请号：US16404996

申请日：2019-05-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-sic YOON ,  Dong-oh KIM ,  Je-min PARK ,  Ki-seok LEE

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/66

Abstract: An integrated circuit device includes a gate stack structure on a base layer, the gate stack structure having a gate insulating layer with a first dielectric layer on the base layer and having first relative permittivity, and a gate structure on the gate insulating layer, and a gate spacer structure on opposite side walls of the gate stack structure and on the base layer, the gate spacer structure including a buried dielectric layer buried in a recess hole of the gate insulating layer at a lower portion of the gate spacer structure on the base layer, and the buried dielectric layer including a same material as the first dielectric layer.

公开(公告)号：US20180350818A1

公开(公告)日：2018-12-06

申请号：US15884504

申请日：2018-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-sic YOON ,  Ki-seok LEE ,  Jung-hyun KIM ,  Je-min PARK

IPC: H01L27/108

CPC classification number: H01L27/10888 ,  H01L21/02697 ,  H01L21/768 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor device includes first wiring line patterns on a support layer, second wiring line patterns on the first wiring line patterns, and a multiple insulation pattern. The first wiring line patterns extend in a first direction and are spaced apart from each other in a second direction. The support layer includes first contact hole patterns between the first wiring line patterns that are spaced apart from each other in the first and second directions. The second wiring line patterns extend in the second direction perpendicular and are spaced apart from each other in the first direction. The multiple insulation pattern is on an upper surface of the support layer where the first contact hole patterns are not formed, arranged in a third direction perpendicular to the first direction and the second direction, and between the first wiring line patterns and the second wiring line patterns.

公开(公告)号：US20180175143A1

公开(公告)日：2018-06-21

申请号：US15833031

申请日：2017-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-sic YOON ,  Ki-seok Lee ,  Ki-wook Jung ,  Dong-oh Kim ,  Ho-in Lee ,  Je-min Park ,  Seok-han Park ,  Augustin Hong ,  Ju-yeon Jang ,  Hyeon-ok Jung ,  Yu-jin Seo

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/762

CPC classification number: H01L29/0649 ,  H01L21/0206 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/4236

Abstract: A semiconductor device including a substrate with a first trench, a first insulation liner on inner flanks of the first trench, and a second insulation liner on inner flanks of a first sub trench, the first insulation trench defined by the first insulation liner in the first trench, a top level of the second insulation liner that adjoins the inner flanks of the first sub trench in a direction perpendicular to a top surface of the substrate being different from the top surface of the substrate outside the first trench, may be provided.