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公开(公告)号：US20230099986A1
公开(公告)日：2023-03-30
申请号：US17943551
申请日：2022-09-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Juyun LEE , Hanseok KIM , Jiyoung KIM , Jaehyun PARK , Hyeonju LEE , Kangjik KIM , Sunggeun KIM , Seuk SON , Hobin SONG , Nakwon LEE
Abstract: An apparatus for generating an output signal having a waveform that is repeated every period, includes a storage configured to store values corresponding to the waveform in a portion of a period of the output signal, a counter configured to generate a first index of a sample included in the output signal, a controller configured to generate at least one control signal based on the first index and the period of the output signal, and a calculation circuit configured to generate the output signal by calculating an output from the storage based on the at least one control signal.
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2.发明公开公开(公告)号：US20230421343A1
公开(公告)日：2023-12-28
申请号：US18243442
申请日：2023-09-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Juyun LEE , Vishnu Kalyanamahadevi Gopalan Jawarlal , Kang Jik KIM , Hyo Gyuem RHEW , Jae Hyun PARK
CPC classification number: H04L7/0016 , H03L7/0807
Abstract: A clock frequency divider circuit and a receiver are provided. The clock frequency divider circuit includes a reset retimer circuit configured to receive a reset signal and a clock signal, output a reset buffer signal of a differential signal pair obtained by buffering the reset signal, and output a reset synchronization signal obtained by synchronizing the reset signal with the clock signal, a clock buffer circuit configured to receive the clock signal and the reset synchronization signal and output a clock buffer signal of a differential signal pair obtained by buffering the clock signal, and an IQ divider circuit configured to output first through fourth output signals having different phases based on the reset buffer signal and the clock buffer signal.
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公开(公告)号：US20230138296A1
公开(公告)日：2023-05-04
申请号：US17669262
申请日：2022-02-10
Applicant: Samsung Electronics Co., Ltd.
Inventor： Juyun LEE , Vishnu Kalyanamahadevi Gopalan Jawarlal , Kang Jik KIM , Hyo Gyuem RHEW , Jae Hyun PARK
Abstract: A clock frequency divider circuit and a receiver are provided. The clock frequency divider circuit includes a reset retimer circuit configured to receive a reset signal and a clock signal, output a reset buffer signal of a differential signal pair obtained by buffering the reset signal, and output a reset synchronization signal obtained by synchronizing the reset signal with the clock signal, a clock buffer circuit configured to receive the clock signal and the reset synchronization signal and output a clock buffer signal of a differential signal pair obtained by buffering the clock signal, and an IQ divider circuit configured to output first through fourth output signals having different phases based on the reset buffer signal and the clock buffer signal.
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