公开(公告)号：US20210183862A1

公开(公告)日：2021-06-17

申请号：US17038355

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-hoon SON ,  Jae Hoon KIM ,  Kwang-Ho PARK ,  Seungjae JUNG

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285 ,  H01L29/66

Abstract: A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.

公开(公告)号：US20210125991A1

公开(公告)日：2021-04-29

申请号：US16923572

申请日：2020-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hoon KIM ,  Kwang-Ho PARK ,  Yong-Hoon SON ,  Hyunji SONG ,  Gyeonghee LEE ,  Seungjae JUNG

IPC: H01L27/108 ,  G11C11/4097

Abstract: A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.

公开(公告)号：US20220254783A1

公开(公告)日：2022-08-11

申请号：US17731611

申请日：2022-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hoon KIM ,  Kwang-Ho PARK ,  Yong-Hoon SON ,  Hyunji SONG ,  Gyeonghee LEE ,  Seungjae JUNG

IPC: H01L27/108 ,  G11C11/4097

Abstract: A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.

公开(公告)号：US20220208768A1

公开(公告)日：2022-06-30

申请号：US17699839

申请日：2022-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Jae JUNG ,  Jae Hoon KIM ,  Kwang-Ho PARK ,  Yong-Hoon SON

IPC: H01L27/108

Abstract: A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.

公开(公告)号：US20210257368A1

公开(公告)日：2021-08-19

申请号：US17038606

申请日：2020-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Jae JUNG ,  Jae Hoon KIM ,  Kwang-Ho PARK ,  Yong-hoon SON

IPC: H01L27/108 ,  H01L27/13

Abstract: A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.

公开(公告)号：US20210134800A1

公开(公告)日：2021-05-06

申请号：US16898640

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-Ho PARK ,  Jae Hoon KIM ,  Yong-Hoon SON ,  Seung Jae JUNG

IPC: H01L27/108

Abstract: A semiconductor memory device including first-first conductive lines on a substrate; second-first conductive lines on the first-first conductive lines; first contacts connected to the first-first conductive lines; and second contacts connected to the second-first conductive lines, wherein the first-first conductive lines protrude in a first direction beyond the second-first conductive lines; the first-first conductive lines include first regions having a first thickness, second regions having a second thickness, the second thickness being greater than the first thickness, and third regions having a third thickness, the third thickness being smaller than the first thickness and smaller than the second thickness, and the second regions of the first-first conductive lines are between the first regions of the first-first conductive lines and the third regions of the first-first conductive lines.