Abstract:
A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.
Abstract:
A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.
Abstract:
A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.
Abstract:
A semiconductor memory device including first-first conductive lines on a substrate; second-first conductive lines on the first-first conductive lines; first contacts connected to the first-first conductive lines; and second contacts connected to the second-first conductive lines, wherein the first-first conductive lines protrude in a first direction beyond the second-first conductive lines; the first-first conductive lines include first regions having a first thickness, second regions having a second thickness, the second thickness being greater than the first thickness, and third regions having a third thickness, the third thickness being smaller than the first thickness and smaller than the second thickness, and the second regions of the first-first conductive lines are between the first regions of the first-first conductive lines and the third regions of the first-first conductive lines.
Abstract:
A magnetic memory device includes a substrate, a tunnel barrier pattern on the substrate, a first magnetic pattern and a second magnetic pattern spaced apart from each other with the tunnel barrier pattern therebetween, and a short preventing pattern spaced apart from the tunnel barrier pattern with the second magnetic pattern therebetween. The short preventing pattern includes at least two oxide layers and at least two metal layers, which are alternately stacked.
Abstract:
Provided is a communication method of a content requester to provide content in a Content-Centric Network (CCN). The method is based on a content name, including generating a content request packet including an identifier indicating a content request based on a predetermined time unit to request content, transmitting the generated content request packet, and receiving segments of the content that correspond to the predetermined time unit. Also provided are corresponding communication methods of a content provider and a node in the CCN.
Abstract:
A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.
Abstract:
A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.
Abstract:
A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.
Abstract:
A first memory device includes a first magnetoresistive cell having a plurality of deposition layers. A second memory device includes a second magnetoresistive cell having a plurality of deposition layers. Each of the plurality of deposition layers of the second magnetoresistive cell corresponds to one of the plurality of deposition layers of the first magnetoresistive cell. One of the plurality of deposition layers of the second magnetoresistive cell is thinner than a corresponding deposition layer of the plurality of deposition layers of the first magnetoresistive cell.