公开(公告)号：US20230005948A1

公开(公告)日：2023-01-05

申请号：US17940441

申请日：2022-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon SON ,  Jae Hoon KIM ,  Kwang-ho PARK ,  Hyunji SONG ,  Gyeonghee LEE ,  Seungjae JUNG

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L23/528 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11582

Abstract: A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.

公开(公告)号：US20140162440A1

公开(公告)日：2014-06-12

申请号：US14082657

申请日：2013-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Ho Kim ,  Daehyun JANG ,  Myoungbum LEE ,  Kihyun HWANG ,  Sangryol YANG ,  Yong-Hoon SON ,  Ju-Eun KIM ,  Sunghae LEE ,  Dongwoo KIM ,  JinGyun KIM

IPC: H01L27/115 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/02675 ,  H01L21/30604 ,  H01L21/324 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/7926

Abstract: Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.

Abstract translation: 可以提供形成半导体器件的方法。 形成半导体器件的方法可以包括图案化第一和第二材料层以形成暴露衬底的第一穿透区域。 该方法可以包括在衬底上的第一至区域中以及在第一和第二材料层的侧壁上形成第一半导体层。 在一些实施例中，该方法可以包括形成填充第一半导体层上的第一通过区域的掩埋层。 在一些实施例中，该方法可以包括移除掩埋层的一部分以在第一和第二材料层的侧壁之间形成第二穿透区域。 此外，该方法可以包括在第二通过区域中形成第二半导体层。

公开(公告)号：US20230031207A1

公开(公告)日：2023-02-02

申请号：US17963591

申请日：2022-10-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon SON ,  Jae Hoon KIM ,  Kwang-ho PARK ,  Seungjae JUNG

IPC: H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/306 ,  H01L21/285

Abstract: A semiconductor memory device includes a stack structure comprising a plurality of layers vertically stacked on a substrate, each layer including a semiconductor pattern, a gate electrode extending in a first direction on the semiconductor pattern, and a data storage element electrically connected to the semiconductor pattern, a plurality of vertical insulators penetrating the stack structure, the vertical insulators arranged in the first direction, and a bit line provided at a side of the stack structure and extending vertically. The bit line electrically connects the semiconductor patterns which are stacked. Each of the vertical insulators includes first and second vertical insulators adjacent to each other. The gate electrode includes a connection portion disposed between the first and second vertical insulators.

公开(公告)号：US20220262814A1

公开(公告)日：2022-08-18

申请号：US17738516

申请日：2022-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon SON ,  Hyung Joon KIM ,  Hyun Jung LEE

IPC: H01L27/11565 ,  H01L27/108

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a first semiconductor pattern that is on a substrate and that includes a first end and a second end that face each other, a first conductive line that is adjacent to a lateral surface of the first semiconductor pattern between the first and second ends and that is perpendicular to a top surface of the substrate, a second conductive line that is in contact with the first end of the first semiconductor pattern, is spaced part from the first conductive line, and is parallel to the top surface of the substrate, and a data storage pattern in contact with the second end of the first semiconductor pattern. The first conductive line has a protrusion that protrudes adjacent to the lateral surface of the first semiconductor pattern.

公开(公告)号：US20210125991A1

公开(公告)日：2021-04-29

申请号：US16923572

申请日：2020-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hoon KIM ,  Kwang-Ho PARK ,  Yong-Hoon SON ,  Hyunji SONG ,  Gyeonghee LEE ,  Seungjae JUNG

IPC: H01L27/108 ,  G11C11/4097

Abstract: A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.

公开(公告)号：US20210082941A1

公开(公告)日：2021-03-18

申请号：US16857507

申请日：2020-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon SON ,  Jae Hoon KIM ,  Kwang-ho PARK ,  Hyunji SONG ,  Gyeonghee LEE ,  Seungjae JUNG

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.

公开(公告)号：US20230114139A1

公开(公告)日：2023-04-13

申请号：US17900172

申请日：2022-08-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon SON ,  Joon Sung KIM ,  Suk Kang SUNG ,  Gil Sung LEE ,  Jong-Min LEE

IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

Abstract: A semiconductor memory device may include a cell substrate including a cell array region and an extension region, a first mold structure on the cell substrate, a second mold structure on the first mold structure, a channel structure passing through the first and second mold structures on the cell array region, and a cell contact structure passing through the first and second mold structures on the extension region. The first mold structure and the second mold structure respectively include first gate electrodes and second gate electrodes sequentially stacked on the cell array region and stacked in a stepwise manner on the extension region. The cell contact structure includes a lower conductive pattern connected to one of the first gate electrodes, an upper conductive pattern connected to one of the second gate electrodes, and an insulating pattern separating the lower conductive pattern from the upper conductive pattern.

公开(公告)号：US20220254783A1

公开(公告)日：2022-08-11

申请号：US17731611

申请日：2022-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hoon KIM ,  Kwang-Ho PARK ,  Yong-Hoon SON ,  Hyunji SONG ,  Gyeonghee LEE ,  Seungjae JUNG

IPC: H01L27/108 ,  G11C11/4097

Abstract: A semiconductor memory device may include a bit line extending in a first direction, a first conductive pattern extending in a second direction intersecting the first direction, a semiconductor pattern connecting the bit line and the first conductive pattern, a second conductive pattern including an insertion portion in the first conductive pattern, and a dielectric layer between the first conductive pattern and the second conductive pattern. The insertion portion of the second conductive pattern may have a width which increases as a distance from the semiconductor pattern increases.

公开(公告)号：US20220208768A1

公开(公告)日：2022-06-30

申请号：US17699839

申请日：2022-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Jae JUNG ,  Jae Hoon KIM ,  Kwang-Ho PARK ,  Yong-Hoon SON

IPC: H01L27/108

Abstract: A semiconductor device includes a bit line extending in a first direction, a gate electrode extending in a second direction, and a semiconductor pattern extending in a third direction and connected to the bit line, and a capacitor. The capacitor includes a first electrode connected to the semiconductor pattern and a dielectric film between the first and second electrodes. The first or the second direction is perpendicular to an upper surface of the substrate. The first electrode includes an upper and a lower plate region parallel to the upper surface of the substrate, and a connecting region which connects the upper and the lower plate regions. The upper and the lower plate regions of the first electrode include an upper and a lower surface facing each other. The dielectric film extends along the upper and the lower surfaces of the upper and lower plate regions of the first electrode.

公开(公告)号：US20210134800A1

公开(公告)日：2021-05-06

申请号：US16898640

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-Ho PARK ,  Jae Hoon KIM ,  Yong-Hoon SON ,  Seung Jae JUNG

IPC: H01L27/108

Abstract: A semiconductor memory device including first-first conductive lines on a substrate; second-first conductive lines on the first-first conductive lines; first contacts connected to the first-first conductive lines; and second contacts connected to the second-first conductive lines, wherein the first-first conductive lines protrude in a first direction beyond the second-first conductive lines; the first-first conductive lines include first regions having a first thickness, second regions having a second thickness, the second thickness being greater than the first thickness, and third regions having a third thickness, the third thickness being smaller than the first thickness and smaller than the second thickness, and the second regions of the first-first conductive lines are between the first regions of the first-first conductive lines and the third regions of the first-first conductive lines.