公开(公告)号：US20230186960A1

公开(公告)日：2023-06-15

申请号：US17852593

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hijung Kim ,  Kwangchol Choe ,  Kwangsook Noh ,  Jaepil Lee

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C8/14 ,  H03K19/017

CPC classification number: G11C7/222 ,  G11C7/12 ,  G11C7/1039 ,  G11C8/14 ,  H03K19/01742

Abstract: A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.

公开(公告)号：US12237048B2

公开(公告)日：2025-02-25

申请号：US17852593

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hijung Kim ,  Kwangchol Choe ,  Kwangsook Noh ,  Jaepil Lee

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C8/14 ,  H03K19/017

Abstract: A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.