公开(公告)号：US12237048B2

公开(公告)日：2025-02-25

申请号：US17852593

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hijung Kim ,  Kwangchol Choe ,  Kwangsook Noh ,  Jaepil Lee

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C8/14 ,  H03K19/017

Abstract: A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.

公开(公告)号：US12183390B2

公开(公告)日：2024-12-31

申请号：US17953524

申请日：2022-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hijung Kim ,  Jung Min You ,  Seong-Jin Cho

IPC: G11C8/00 ,  G11C11/408 ,  G11C11/4096 ,  G11C17/16

Abstract: Disclosed is a memory device which includes a memory core that includes a plurality of memory cells, and control logic that receives a first active command and a first row address from an external device and activates memory cells corresponding to the first row address from among the plurality of memory cells in response to the first active command. The control logic includes registers and counters. The control logic records the first row address in one of the registers, counts an activation count of the first row address by using a first counter of the counters, and counts a lifetime count of the first row address by using a second counter of the counters.

公开(公告)号：US20230186960A1

公开(公告)日：2023-06-15

申请号：US17852593

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hijung Kim ,  Kwangchol Choe ,  Kwangsook Noh ,  Jaepil Lee

IPC: G11C7/22 ,  G11C7/10 ,  G11C7/12 ,  G11C8/14 ,  H03K19/017

CPC classification number: G11C7/222 ,  G11C7/12 ,  G11C7/1039 ,  G11C8/14 ,  H03K19/01742

Abstract: A memory device includes a memory cell array having memory cells connected to wordlines and bitlines, and a clock buffer receiving a clock signal for performing a read operation or a write operation on at least one of the memory cells. The clock buffer includes a plurality of serially connected clock repeaters, and the plurality of clock repeaters have at least one pair of clock repeaters having different imbalanced driving capabilities.

公开(公告)号：US12217786B2

公开(公告)日：2025-02-04

申请号：US18613361

申请日：2024-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hijung Kim ,  Hoyoun Kim ,  Jungmin You ,  Seongjin Cho

IPC: G11C11/00 ,  G06F7/544 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4094

Abstract: A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.

公开(公告)号：US11961550B2

公开(公告)日：2024-04-16

申请号：US17735542

申请日：2022-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hijung Kim ,  Hoyoun Kim ,  Jungmin You ,  Seongjin Cho

IPC: G11C11/00 ,  G06F7/544 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4094

CPC classification number: G11C11/40622 ,  G06F7/5443 ,  G11C11/40611 ,  G11C11/4085 ,  G11C11/4094

Abstract: A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.