公开(公告)号：US20210226617A1

公开(公告)日：2021-07-22

申请号：US17021367

申请日：2020-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung RHO ,  Jang-Woo RYU ,  Hyunah AN ,  Hangi JUNG

IPC: H03K3/356

Abstract: Disclosed is a level shifter. The level shifter includes a level shifting circuit, a first adjusting circuit, and a second adjusting circuit. The level shifting circuit determines whether to output a first current from a supply voltage line to an output node based on a voltage level of a first node and determines whether to output a second current from the supply voltage line to a third node based on a voltage level of a second node. The first adjusting circuit blocks an output of a third current from the third node to the first node when a clock signal having a first voltage level is received. The second adjusting circuit outputs a fourth current from the first node to a ground voltage line when the clock signal having the first voltage level is received.

公开(公告)号：US20190237390A1

公开(公告)日：2019-08-01

申请号：US16263408

申请日：2019-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung RHO ,  Chisung OH ,  Kyomin SOHN ,  Yong-Ki KIM ,  Jong-Ho MOON ,  SeungHan WOO ,  Jaeyoun YOUN

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538

Abstract: A semiconductor device includes first to M-th semiconductor dies stacked in a first direction. Each of the first to M-th semiconductor dies includes a substrate, first to K-th through silicon vias passing through the substrate in the first direction, and a first circuit to receive power through a power supply line electrically connected to the first through silicon via. Each of first to K-th through silicon vias of the N-th semiconductor die is electrically connected to a through silicon via of first to K-th through silicon vias of the (N+1)-th semiconductor die that is spaced apart therefrom in a plan view.