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    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
    半导体存储器件及其操作方法

    公开(公告)号：US20140211577A1

    公开(公告)日：2014-07-31

    申请号：US14141233

    申请日：2013-12-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jang-Woo RYU ,  Young-Dae LEE

    IPC: G11C7/02

    CPC classification number: G11C11/40626 ,  G11C11/4074

    Abstract: A method of operating a semiconductor memory device is disclosed. The method may include receiving an access command, applying a first voltage to a selected word line of the semiconductor memory device for a period of time in response to receiving the access command, applying a second voltage to word lines adjacent to the selected word line before and after the period of time, and applying a third voltage to the word lines adjacent to the selected word line for the period of time, a voltage level of the third voltage greater than the second voltage. The applying the third voltage may occur when the semiconductor memory device is operated at a temperature below the predetermined temperature.

    Abstract translation: 公开了一种操作半导体存储器件的方法。 该方法可以包括接收访问命令，响应于接收到访问命令，将半导体存储器件的选定字线施加第一电压一段时间，将第二电压施加到与所选字线相邻的字线之前 并且在所述时间段之后，并且对于与所选择的字线相邻的字线在一段时间内施加第三电压，所述第三电压的电压电平大于所述第二电压。 当半导体存储器件在低于预定温度的温度下工作时，施加第三电压可能发生。

    ELECTRONIC DEVICE INCLUDING LEVEL SHIFTER
    4.
    发明申请
    ELECTRONIC DEVICE INCLUDING LEVEL SHIFTER 有权

    公开(公告)号：US20210226617A1

    公开(公告)日：2021-07-22

    申请号：US17021367

    申请日：2020-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Soojung RHO ,  Jang-Woo RYU ,  Hyunah AN ,  Hangi JUNG

    IPC: H03K3/356

    Abstract: Disclosed is a level shifter. The level shifter includes a level shifting circuit, a first adjusting circuit, and a second adjusting circuit. The level shifting circuit determines whether to output a first current from a supply voltage line to an output node based on a voltage level of a first node and determines whether to output a second current from the supply voltage line to a third node based on a voltage level of a second node. The first adjusting circuit blocks an output of a third current from the third node to the first node when a clock signal having a first voltage level is received. The second adjusting circuit outputs a fourth current from the first node to a ground voltage line when the clock signal having the first voltage level is received.

    SEMICONDUCTOR MEMORY DEVICES
    7.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES 审中-公开
    半导体存储器件

    公开(公告)号：US20140331006A1

    公开(公告)日：2014-11-06

    申请号：US14208339

    申请日：2014-03-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hoi-Ju CHUNG ,  Chul-Sung PARK ,  Tae-Seong JANG ,  Gong-Heum HAN ,  Jang-Woo RYU

    IPC: G11C7/10

    CPC classification number: G11C7/1096 ,  G11C7/1006 ,  G11C7/1009

    Abstract: A semiconductor memory device includes a memory cell array, a data inversion/mask interface and a write circuit. The data inversion/mask interface receives a data block including a plurality of unit data, each of the plurality of unit data having a first data size, and the data inversion/mask interface selectively enables each data mask signal associated with each of the plurality of unit data based on a number of first data bits in a second data size of each unit data. The second data size is smaller than a first data size of the unit data. The write circuit receives the data block and performs a masked write operation that selectively writes each of the plurality of unit data in the memory cell array in response to the data mask signal.

    Abstract translation: 半导体存储器件包括存储单元阵列，数据反转/掩模接口和写入电路。 数据反转/掩模接口接收包括多个单元数据的数据块，多个单元数据中的每一个具有第一数据大小，并且数据反转/掩码接口选择性地启用与多个单元数据中的每一个相关联的每个数据掩码信号 基于每个单位数据的第二数据大小中的第一数据位的数量的单元数据。 第二数据大小小于单位数据的第一数据大小。 写入电路接收数据块并执行屏蔽写入操作，其响应于数据屏蔽信号选择性地将多个单元数据中的每一个写入存储单元阵列。

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