公开(公告)号：US20160343424A1

公开(公告)日：2016-11-24

申请号：US15226310

申请日：2016-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hangi JUNG

IPC: G11C11/4076 ,  G11C11/4072

CPC classification number: G11C7/22 ,  G11C5/148 ,  G11C7/02 ,  G11C7/1057 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4076 ,  G11C2207/2272

Abstract: An operation control method of a semiconductor memory device includes executing a Delay Locked Loop (DLL) locking in response to a DLL reset signal and measuring a loop delay of a DLL. The operation control method further includes storing measured loop delay information and DLL locking information; and performing a delay control of a command path using the stored loop delay information and DLL locking information independent of the DLL, during a latency control operation.

Abstract translation: 半导体存储器件的操作控制方法包括响应于DLL复位信号执行延迟锁定环（DLL）锁定并测量DLL的环路延迟。 操作控制方法还包括存储测量的环路延迟信息和DLL锁定信息; 以及在等待时间控制操作期间，使用存储的循环延迟信息和与DLL无关的DLL锁定信息执行命令路径的延迟控制。

公开(公告)号：US20210226617A1

公开(公告)日：2021-07-22

申请号：US17021367

申请日：2020-09-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung RHO ,  Jang-Woo RYU ,  Hyunah AN ,  Hangi JUNG

IPC: H03K3/356

Abstract: Disclosed is a level shifter. The level shifter includes a level shifting circuit, a first adjusting circuit, and a second adjusting circuit. The level shifting circuit determines whether to output a first current from a supply voltage line to an output node based on a voltage level of a first node and determines whether to output a second current from the supply voltage line to a third node based on a voltage level of a second node. The first adjusting circuit blocks an output of a third current from the third node to the first node when a clock signal having a first voltage level is received. The second adjusting circuit outputs a fourth current from the first node to a ground voltage line when the clock signal having the first voltage level is received.

公开(公告)号：US20210141747A1

公开(公告)日：2021-05-13

申请号：US17008121

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Su JEONG ,  Hangi JUNG ,  Wangsoo Kim ,  Hae Young CHUNG

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.

公开(公告)号：US20230131945A1

公开(公告)日：2023-04-27

申请号：US18089148

申请日：2022-12-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heon Su JEONG ,  Hangi JUNG ,  Wangsoo KIM ,  Hae Young CHUNG

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/22 ,  G11C7/10 ,  G11C8/18

Abstract: A memory device of a memory module includes a CA buffer that receives a command/address (CA) signal through a bus shared by a memory device different from the memory device of the memory module, and a calibration logic circuit that identifies location information of the memory device on the bus. The memory device recognizes its own location on a bus in a memory module to perform self-calibration, and thus, the memory device appropriately operates even under an operation condition varying depending on a location in the memory module.