公开(公告)号：US20200075458A1

公开(公告)日：2020-03-05

申请号：US16366267

申请日：2019-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-suk LEE ,  Hak-seung Lee ,  Dong-chan Lim ,  Tae-seong Kim ,  Kwang-jin Moon

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/532 ,  H01L23/31 ,  H01L23/522 ,  H01L25/18

Abstract: Semiconductor chips and methods of manufacturing the same are provided. The semiconductor chip includes a substrate, an interlayer insulation layer including a bottom interlayer insulation layer on an upper surface of the substrate and a top interlayer insulation layer on the bottom interlayer insulation layer, an etch stop layer between the bottom interlayer insulation layer and the top interlayer insulation layer, a landing pad on the interlayer insulation layer, and a through via connected to the landing pad through the substrate, the interlayer insulation layer, and the etch stop layer. The etch stop layer is isolated from direct contact with the landing pad.

公开(公告)号：US11069597B2

公开(公告)日：2021-07-20

申请号：US16366267

申请日：2019-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-suk Lee ,  Hak-seung Lee ,  Dong-chan Lim ,  Tae-seong Kim ,  Kwang-jin Moon

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532 ,  H01L25/18

Abstract: Semiconductor chips and methods of manufacturing the same are provided. The semiconductor chip includes a substrate, an interlayer insulation layer including a bottom interlayer insulation layer on an upper surface of the substrate and a top interlayer insulation layer on the bottom interlayer insulation layer, an etch stop layer between the bottom interlayer insulation layer and the top interlayer insulation layer, a landing pad on the interlayer insulation layer, and a through via connected to the landing pad through the substrate, the interlayer insulation layer, and the etch stop layer. The etch stop layer is isolated from direct contact with the landing pad.

公开(公告)号：US09805818B2

公开(公告)日：2017-10-31

申请号：US15354304

申请日：2016-11-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-seong Kim ,  Cheol-ha Lee

IPC: G11C17/16 ,  G11C17/18 ,  H01L27/112 ,  H01L23/525

CPC classification number: G11C17/18 ,  G11C17/16 ,  H01L23/5256 ,  H01L27/11206 ,  H01L28/00

Abstract: A fuse memory comprising a discharge circuit is provided. The fuse memory includes a fuse cell array comprising fuse cells connected to read word lines, programs word lines, and bit lines arranged in rows and columns; and at least one discharge circuit arranged in each of the rows. The discharge circuit discharges a voltage level of a program word line of the fuse cells selected in a read mode to a ground voltage.

公开(公告)号：US20170053716A1

公开(公告)日：2017-02-23

申请号：US15232201

申请日：2016-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-seong Kim

IPC: G11C29/00 ,  G11C17/18 ,  G11C29/04 ,  G11C17/16

CPC classification number: G11C29/24 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027

Abstract: In a one-time programmable (OTP) memory and a method of testing the same. The OTP memory includes an OTP cell array comprising OTP cells which are activated by an address received from a source external to the OTP memory and which OTP cells are unprogrammed. A test cell array includes a first test row having unprogrammed first test cells and a second test row having mask-programmed second test cells, and sharing bit lines extending in a column direction with the OTP cell array. The first test cells and second test cells are accessible during testing of the OTP cell array.

Abstract translation: 在一次性可编程（OTP）存储器和测试方法中。 OTP存储器包括OTP单元阵列，其包括由从OTP存储器外部的源接收的地址激活的OTP单元，并且哪些OTP单元未被编程。 测试单元阵列包括具有未编程的第一测试单元的第一测试行和具有掩模编程的第二测试单元的第二测试行，并且与OTP单元阵列共享沿列方向延伸的位线。 在测试OTP单元阵列期间可以访问第一测试单元和第二测试单元。