公开(公告)号：US20240203873A1

公开(公告)日：2024-06-20

申请号：US18065632

申请日：2022-12-14

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： SHU HUI LEE ,  JUAN BOON TAN ,  JIANXUN SUN ,  MYO AUNG MAUNG ,  HARI BALAN

IPC: H01L23/525 ,  H01L27/01

CPC classification number: H01L23/5252 ,  H01L27/01 ,  H01L28/00

Abstract: An antifuse device has a first contact structure and a second contact structure in a substrate. The first contact structure has a first contact side adjoining a second contact side and forming a first contact corner having an acute angle. The second contact structure is spaced from and not electrically connected to the first contact structure. The antifuse device further includes a first dummy structure in the substrate, adjacent to the first contact structure. The first dummy structure has a first dummy side nearest to and spaced from the first contact side of the first contact structure.

公开(公告)号：US12002745B2

公开(公告)日：2024-06-04

申请号：US17544693

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Mathew J. Manusharow ,  Krishna Bharath ,  William J. Lambert ,  Robert L. Sankman ,  Aleksandar Aleksov ,  Brandon M. Rawlings ,  Feras Eid ,  Javier Soto Gonzalez ,  Meizi Jiao ,  Suddhasattwa Nad ,  Telesphor Kamgaing

IPC: H05K1/02 ,  H01F17/00 ,  H01F17/06 ,  H01F27/28 ,  H01F27/40 ,  H01F41/04 ,  H01G4/18 ,  H01G4/252 ,  H01G4/30 ,  H01G4/33 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66 ,  H01L49/02

CPC classification number: H01L23/49838 ,  H01F17/0006 ,  H01F27/2804 ,  H01F27/40 ,  H01F41/041 ,  H01G4/33 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/66 ,  H01L28/00 ,  H01L28/10 ,  H01L28/60 ,  H01F2027/2809 ,  H01L2223/6661

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.

公开(公告)号：US11924573B2

公开(公告)日：2024-03-05

申请号：US16085847

申请日：2017-03-15

Applicant: TRUSTEES OF DARTMOUTH COLLEGE

Inventor： Eric R. Fossum ,  Saleh Masoodian

IPC: H04N25/79 ,  H01L27/00 ,  H01L27/146 ,  H01L49/02 ,  H04N25/75 ,  H04N25/77

CPC classification number: H04N25/79 ,  H01L27/00 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L28/00 ,  H04N25/75 ,  H04N25/77

Abstract: Some embodiments provide a Quanta Image Sensor (QIS) comprising 3D vertically-stacked photosensor array and readout circuitry. In some embodiments, an imaging array comprises a plurality of single-bit or multi-bit jots, and readout circuitry in electrical communication with the imaging array and configured to quantize, for each jot, an analog signal corresponding to the electrical signal of the jot, wherein the imaging system is configured as a 3D vertically integrated circuit with the imaging array stacked vertically above the readout circuitry. The imaging array may be configured as an array of clusters with respect to the readout circuitry, each cluster configured as an array of n by m jots. The imaging array may include a further image processing circuitry layer disposed below the readout circuitry layer. Neighboring layers may be implemented on separate substrates and/or in a common substrate.

公开(公告)号：US11870438B2

公开(公告)日：2024-01-09

申请号：US17752673

申请日：2022-05-24

Applicant: Schottky LSI, Inc.

Inventor： Augustine Wei-Chun Chang ,  Pierre Dermy

IPC: H03K19/09 ,  H03K19/0956 ,  H01L25/065 ,  H01L27/02 ,  H01L27/105 ,  H01L27/118 ,  H01L49/02 ,  H01L31/032 ,  H01L31/0376 ,  H01L31/072 ,  H01L31/074 ,  H03K19/017 ,  H03K19/0948 ,  H03K19/17728 ,  H10B12/00 ,  H10B20/00 ,  H10B41/40 ,  H10B41/49

CPC classification number: H03K19/0956 ,  H01L25/065 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11807 ,  H01L28/00 ,  H01L31/032 ,  H01L31/0376 ,  H01L31/072 ,  H01L31/074 ,  H03K19/01707 ,  H03K19/0948 ,  H03K19/17728 ,  H10B12/50 ,  H10B20/00 ,  H10B20/38 ,  H10B20/60 ,  H10B20/65 ,  H10B41/40 ,  H10B41/49 ,  H01L28/20 ,  H01L2924/0002 ,  Y02E10/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.

公开(公告)号：US20230368843A1

公开(公告)日：2023-11-16

申请号：US18225879

申请日：2023-07-25

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli HARARI

IPC: G11C16/04 ,  H01L21/02 ,  G11C11/56 ,  G11C16/10 ,  H01L29/423 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L21/768 ,  H01L29/66 ,  H01L29/16 ,  H01L29/06 ,  H01L29/786 ,  H01L29/51 ,  H01L21/3213 ,  H01L29/04 ,  G11C16/34 ,  G11C16/28 ,  H01L21/28 ,  G11C16/26 ,  H01L29/792 ,  H01L27/06

CPC classification number: G11C16/0466 ,  H01L21/02164 ,  H01L21/0217 ,  G11C11/5635 ,  G11C16/0491 ,  G11C16/10 ,  H01L29/4234 ,  G11C16/0416 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/1037 ,  H01L21/02532 ,  H01L21/76892 ,  H01L29/66833 ,  H01L29/16 ,  H01L29/0649 ,  H01L29/78642 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6675 ,  H01L21/02595 ,  H01L21/32133 ,  H01L28/00 ,  H10B43/10 ,  H10B43/35 ,  H01L29/04 ,  G11C16/3427 ,  H10B43/27 ,  G11C16/28 ,  G11C16/0483 ,  H01L29/40117 ,  G11C16/26 ,  H01L29/7926 ,  H10B43/40 ,  H01L27/0688 ,  G11C11/5628

Abstract: A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.

公开(公告)号：US11749344B2

公开(公告)日：2023-09-05

申请号：US17394249

申请日：2021-08-04

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C16/04 ,  H01L23/528 ,  G11C16/28 ,  H01L29/08 ,  H01L29/16 ,  H01L29/04 ,  H01L29/06 ,  H01L29/786 ,  G11C16/10 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/423 ,  H01L21/28 ,  G11C11/56 ,  G11C16/26 ,  G11C16/34 ,  H01L27/06 ,  H01L29/792 ,  H01L49/02 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/0466 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0416 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3427 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/32133 ,  H01L21/76892 ,  H01L23/528 ,  H01L27/0688 ,  H01L28/00 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6675 ,  H01L29/66833 ,  H01L29/78642 ,  H01L29/7926 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.

公开(公告)号：US11698841B2

公开(公告)日：2023-07-11

申请号：US17585979

申请日：2022-01-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jasbir Singh Nayyar ,  Shashank Srinivasa Nuthakki ,  Rahul Gulati ,  Arun Shrimali

IPC: G06F11/16 ,  G06F11/00 ,  H01L49/02 ,  G06F30/39 ,  H01L23/00

CPC classification number: G06F11/16 ,  G06F11/004 ,  G06F11/1641 ,  G06F30/39 ,  H01L28/00 ,  G06F11/1679 ,  H01L23/562

Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

公开(公告)号：US20230178458A1

公开(公告)日：2023-06-08

申请号：US17643247

申请日：2021-12-08

Applicant: Apple Inc.

Inventor： Kumar Nagarajan ,  Flynn P. Carson ,  Karthik Shanmugam ,  Menglu Li ,  Raymundo M. Camenforte ,  Scott D. Morrison

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/538 ,  H01L23/532 ,  H01L49/02

CPC classification number: H01L23/4952 ,  H01L23/31 ,  H01L23/5381 ,  H01L23/53228 ,  H01L28/00

Abstract: Package structures, modules containing such packages and methods of manufacture. are described. In an embodiment, a package includes a plurality of terminal pads, a plurality of passive components bonded to top sides of the plurality of terminal pads, a die bonded to top sides of the plurality of passive components and a molding compound encapsulating at least the plurality of passive components and the die.

公开(公告)号：US20190244901A1

公开(公告)日：2019-08-08

申请号：US16382478

申请日：2019-04-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Peng ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Yung-Sung Yen

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5286 ,  H01L21/76816 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L28/00

Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method includes forming a plurality of gate structures extending in a first direction over a substrate between a plurality of source/drain regions. A lower power rail is formed extending in a second direction perpendicular to the first direction. A first connection pin is formed to be electrically coupled to one of the plurality of source/drain regions and to the lower power rail. The first connection pin is formed according to a cut mask having cut regions that define opposing ends of the first connection pin. An upper power rail is formed directly over the lower power rail and extending in the second direction. The upper power rail is electrically coupled to the first connection pin.

公开(公告)号：US20190237538A1

公开(公告)日：2019-08-01

申请号：US16378031

申请日：2019-04-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael A. Guillorn ,  Fei Liu ,  Zhen Zhang

IPC: H01L29/06 ,  H01L49/02 ,  H01L29/45 ,  H01L29/78 ,  H01L21/306 ,  H01L21/324 ,  H01L27/11582 ,  H01L21/265 ,  H01L21/283 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L23/528 ,  H01L21/3213

CPC classification number: H01L29/0638 ,  H01L21/265 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/11582 ,  H01L28/00 ,  H01L28/40 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/785

Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure overlying a deep trench capacitor embedded in a substrate and forming a gate stack straddling a body region of the semiconductor fin, source/drain regions are formed in portions the semiconductor fin located on opposite sides of the gate stack by ion implantation. Next, a metal layer is applied over the source/drain region and subsequent annealing consumes entire source/drain regions to provide fully alloyed source/drain regions. A post alloyzation ion implantation is then performed to introduce dopants into the fully alloyed source/drain regions followed by an anneal to segregate the implanted dopants at interfaces between the fully alloyed source/drain regions and the body region of the semiconductor fin.