公开(公告)号：US20130234279A1

公开(公告)日：2013-09-12

申请号：US13780793

申请日：2013-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-jung Kim ,  Seung-pil Ko ,  Yong-june Kim

IPC: H01L21/762 ,  H01L29/861

CPC classification number: H01L21/76232 ,  H01L21/3086 ,  H01L27/1021 ,  H01L27/224 ,  H01L29/861

Abstract: A semiconductor device with buried word line structures and methods of forming the semiconductor device are provided. The semiconductor device includes a plurality of insulating line patterns extending in a direction in a substrate, a plurality of word lines alternately with ones of the plurality of insulating line patterns, the plurality of word lines extending in the direction and comprising a metal, a plurality of first doped regions on respective ones of the plurality of the word lines and between two adjacent ones of the plurality of insulating line patterns, an interlayer insulating film on the plurality of insulating line patterns and the plurality of first doped regions, the interlayer insulating film including a plurality of openings exposing upper surfaces of ones of the plurality of first doped regions and a plurality of second doped regions contacting respective ones of the plurality of first doped regions within the openings.

Abstract translation: 提供具有掩埋字线结构的半导体器件和形成半导体器件的方法。 半导体器件包括沿衬底方向延伸的多个绝缘线图案，多个字线与多个绝缘线图形中的一个交替排列，多个字线沿该方向延伸并且包括金属，多个 的多个绝缘线图形中的相邻的多个绝缘线图案之间的第一掺杂区域和多个绝缘线图案中的相邻两个之间的第一掺杂区域，多个绝缘线图案上的层间绝缘膜和多个第一掺杂区域，层间绝缘膜 包括暴露多个第一掺杂区域中的一个的上表面的多个开口以及与开口内的多个第一掺杂区域中的相应一个接触的多个第二掺杂区域。

公开(公告)号：US08969996B2

公开(公告)日：2015-03-03

申请号：US13780793

申请日：2013-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-jung Kim ,  Seung-pil Ko ,  Yong-june Kim

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/861 ,  H01L21/308 ,  H01L27/102 ,  H01L27/22

CPC classification number: H01L21/76232 ,  H01L21/3086 ,  H01L27/1021 ,  H01L27/224 ,  H01L29/861

Abstract: A semiconductor device with buried word line structures and methods of forming the semiconductor device are provided. The semiconductor device includes a plurality of insulating line patterns extending in a direction in a substrate, a plurality of word lines alternately with ones of the plurality of insulating line patterns, the plurality of word lines extending in the direction and comprising a metal, a plurality of first doped regions on respective ones of the plurality of the word lines and between two adjacent ones of the plurality of insulating line patterns, an interlayer insulating film on the plurality of insulating line patterns and the plurality of first doped regions, the interlayer insulating film including a plurality of openings exposing upper surfaces of ones of the plurality of first doped regions and a plurality of second doped regions contacting respective ones of the plurality of first doped regions within the openings.

Abstract translation: 提供具有掩埋字线结构的半导体器件和形成半导体器件的方法。 半导体器件包括沿衬底方向延伸的多个绝缘线图案，多个字线与多个绝缘线图形中的一个交替排列，多个字线沿该方向延伸并且包括金属，多个 的多个绝缘线图形中的相邻的多个绝缘线图案之间的第一掺杂区域和多个绝缘线图案中的相邻两个之间的第一掺杂区域，多个绝缘线图案上的层间绝缘膜和多个第一掺杂区域，层间绝缘膜 包括暴露多个第一掺杂区域中的一个的上表面的多个开口以及与开口内的多个第一掺杂区域中的相应一个接触的多个第二掺杂区域。