公开(公告)号：US20130234279A1

公开(公告)日：2013-09-12

申请号：US13780793

申请日：2013-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-jung Kim ,  Seung-pil Ko ,  Yong-june Kim

IPC: H01L21/762 ,  H01L29/861

CPC classification number: H01L21/76232 ,  H01L21/3086 ,  H01L27/1021 ,  H01L27/224 ,  H01L29/861

Abstract: A semiconductor device with buried word line structures and methods of forming the semiconductor device are provided. The semiconductor device includes a plurality of insulating line patterns extending in a direction in a substrate, a plurality of word lines alternately with ones of the plurality of insulating line patterns, the plurality of word lines extending in the direction and comprising a metal, a plurality of first doped regions on respective ones of the plurality of the word lines and between two adjacent ones of the plurality of insulating line patterns, an interlayer insulating film on the plurality of insulating line patterns and the plurality of first doped regions, the interlayer insulating film including a plurality of openings exposing upper surfaces of ones of the plurality of first doped regions and a plurality of second doped regions contacting respective ones of the plurality of first doped regions within the openings.

Abstract translation: 提供具有掩埋字线结构的半导体器件和形成半导体器件的方法。 半导体器件包括沿衬底方向延伸的多个绝缘线图案，多个字线与多个绝缘线图形中的一个交替排列，多个字线沿该方向延伸并且包括金属，多个 的多个绝缘线图形中的相邻的多个绝缘线图案之间的第一掺杂区域和多个绝缘线图案中的相邻两个之间的第一掺杂区域，多个绝缘线图案上的层间绝缘膜和多个第一掺杂区域，层间绝缘膜 包括暴露多个第一掺杂区域中的一个的上表面的多个开口以及与开口内的多个第一掺杂区域中的相应一个接触的多个第二掺杂区域。

公开(公告)号：US20190097007A1

公开(公告)日：2019-03-28

申请号：US15914611

申请日：2018-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-hyeok AHN ,  Eun-jung Kim ,  Hui-jung Kim ,  Ki-seok Lee ,  Bong-soo Kim ,  Myeong-dong Lee ,  Sung-hee Han ,  Yoo-sang Hwang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L21/762 ,  H01L21/74

Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

公开(公告)号：US10580876B2

公开(公告)日：2020-03-03

申请号：US15914611

申请日：2018-03-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-hyeok Ahn ,  Eun-jung Kim ,  Hui-jung Kim ,  Ki-seok Lee ,  Bong-soo Kim ,  Myeong-dong Lee ,  Sung-hee Han ,  Yoo-sang Hwang

IPC: H01L29/423 ,  H01L21/74 ,  H01L21/762 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66

Abstract: An integrated circuit device may include a pair of line structures. Each line structure may include a pair of conductive lines extending over a substrate in a first horizontal direction and a pair of insulating capping patterns respectively covering the pair of conductive lines. The integrated circuit device may include a conductive plug between the pair of line structures and a metal silicide film contacting a top surface of the conductive plug between the pair of insulating capping patterns. The conductive plug may have a first width between the pair of conductive lines and a second width between the pair of insulating capping patterns, in a second horizontal direction perpendicular to the first horizontal direction, where the second width is greater than the first width.

公开(公告)号：US09012877B2

公开(公告)日：2015-04-21

申请号：US13684884

申请日：2012-11-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-kyu Lee ,  Seung-pil Ko ,  Yong-jun Kim ,  Eun-jung Kim

IPC: H01L29/02 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/00 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1675 ,  H01L45/1683

Abstract: A semiconductor device includes a first semiconductor layer extending in a first direction on a substrate, a plurality of second semiconductor layers spaced apart in the first direction on the first semiconductor layer, and an insulation layer structure surrounding side walls of the first semiconductor layer and the plurality of second semiconductor layers. The first semiconductor layer may have a first conductivity type, and the plurality of second semiconductor layers may have a second conductivity type.

Abstract translation: 半导体器件包括在衬底上沿第一方向延伸的第一半导体层，在第一半导体层上沿第一方向隔开的多个第二半导体层和围绕第一半导体层的侧壁的绝缘层结构， 多个第二半导体层。 第一半导体层可以具有第一导电类型，并且多个第二半导体层可以具有第二导电类型。

公开(公告)号：US08969996B2

公开(公告)日：2015-03-03

申请号：US13780793

申请日：2013-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-jung Kim ,  Seung-pil Ko ,  Yong-june Kim

IPC: H01L21/00 ,  H01L21/762 ,  H01L29/861 ,  H01L21/308 ,  H01L27/102 ,  H01L27/22

CPC classification number: H01L21/76232 ,  H01L21/3086 ,  H01L27/1021 ,  H01L27/224 ,  H01L29/861

Abstract: A semiconductor device with buried word line structures and methods of forming the semiconductor device are provided. The semiconductor device includes a plurality of insulating line patterns extending in a direction in a substrate, a plurality of word lines alternately with ones of the plurality of insulating line patterns, the plurality of word lines extending in the direction and comprising a metal, a plurality of first doped regions on respective ones of the plurality of the word lines and between two adjacent ones of the plurality of insulating line patterns, an interlayer insulating film on the plurality of insulating line patterns and the plurality of first doped regions, the interlayer insulating film including a plurality of openings exposing upper surfaces of ones of the plurality of first doped regions and a plurality of second doped regions contacting respective ones of the plurality of first doped regions within the openings.

Abstract translation: 提供具有掩埋字线结构的半导体器件和形成半导体器件的方法。 半导体器件包括沿衬底方向延伸的多个绝缘线图案，多个字线与多个绝缘线图形中的一个交替排列，多个字线沿该方向延伸并且包括金属，多个 的多个绝缘线图形中的相邻的多个绝缘线图案之间的第一掺杂区域和多个绝缘线图案中的相邻两个之间的第一掺杂区域，多个绝缘线图案上的层间绝缘膜和多个第一掺杂区域，层间绝缘膜 包括暴露多个第一掺杂区域中的一个的上表面的多个开口以及与开口内的多个第一掺杂区域中的相应一个接触的多个第二掺杂区域。