公开(公告)号：US10911034B2

公开(公告)日：2021-02-02

申请号：US16679794

申请日：2019-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Woo Seo ,  Youngsoo Shin ,  Jinwook Jung

IPC: H03K3/3562 ,  H01L27/02 ,  G01R31/317 ,  G01R31/3185 ,  H03K3/037

Abstract: A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.

公开(公告)号：US20200076410A1

公开(公告)日：2020-03-05

申请号：US16679794

申请日：2019-11-11

Applicant: Samsung Electronics Co., Ltd. ,  Korea Advanced Institute of Science and Technology

Inventor： Jae-Woo SEO ,  Youngsoo Shin ,  Jinwook Jung

IPC: H03K3/3562 ,  G01R31/3185 ,  H01L27/02 ,  G01R31/317

Abstract: A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.

公开(公告)号：US10511293B2

公开(公告)日：2019-12-17

申请号：US16103233

申请日：2018-08-14

Applicant: Samsung Electronics Co., Ltd. ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Jae-Woo Seo ,  Youngsoo Shin ,  Jinwook Jung

IPC: H03K3/3562 ,  H03K3/037 ,  G01R31/317 ,  H01L27/02 ,  G01R31/3185

Abstract: A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.

公开(公告)号：US10593701B2

公开(公告)日：2020-03-17

申请号：US15908253

申请日：2018-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Woo Seo ,  Youngsoo Shin

IPC: H01L27/118 ,  H01L23/528 ,  G06F17/50 ,  H01L27/02

Abstract: A semiconductor device includes a substrate including a PMOSFET region and an NMOSFET region. First active patterns are on the PMOSFET region. Second active patterns are on the NMOSFET region. Gate electrodes intersect the first and second active patterns and extend in a first direction. First interconnection lines are disposed on the gate electrodes and extend in the first direction. The gate electrodes are arranged at a first pitch in a second direction intersecting the first direction. The first interconnection lines are arranged at a second pitch in the second direction. The second pitch is smaller than the first pitch.

公开(公告)号：US20190207593A1

公开(公告)日：2019-07-04

申请号：US16103233

申请日：2018-08-14

Applicant: Samsung Electronics Co., Ltd. ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Jae-Woo SEO ,  Youngsoo Shin ,  Jinwook Jung

IPC: H03K3/3562 ,  H03K3/037 ,  G01R31/3185 ,  H01L27/02 ,  G01R31/317

Abstract: A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.