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    Silicene electronic device
    1.
    发明授权
    Silicene electronic device 有权

    公开(公告)号：US11245021B2

    公开(公告)日：2022-02-08

    申请号：US17028205

    申请日：2020-09-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngtek Oh ,  Jinwook Jung ,  Hyeokshin Kwon ,  Wontaek Seo ,  Insu Jeon

    IPC: H01L29/45 ,  H01L29/786 ,  H01L29/16

    Abstract: A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.

    Silicene electronic device
    2.
    发明授权
    Silicene electronic device 有权

    公开(公告)号：US10818765B2

    公开(公告)日：2020-10-27

    申请号：US16356378

    申请日：2019-03-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngtek Oh ,  Jinwook Jung ,  Hyeokshin Kwon ,  Wontaek Seo ,  Insu Jeon

    IPC: H01L29/45 ,  H01L29/16 ,  H01L29/786

    Abstract: A silicene electronic device includes a silicene material layer. The silicene material layer of the silicene electronic device has a 2D honeycomb structure of silicon atoms, is doped with at least one material of Group I, Group II, Group XVI, and Group XVII, and includes at least one of a p-type dopant region doped with a p-type dopant and an n-type dopant region doped with an n-type dopant. An electrode material layer including a material having a work function lower than the electron affinity of silicene is formed on the silicene material layer.

    TOMOGRAPHIC IMAGE PROCESSING APPARATUS AND METHOD, AND COMPUTER PROGRAM PRODUCT
    6.
    发明申请
    TOMOGRAPHIC IMAGE PROCESSING APPARATUS AND METHOD, AND COMPUTER PROGRAM PRODUCT 审中-公开

    公开(公告)号：US20200163637A1

    公开(公告)日：2020-05-28

    申请号：US16692635

    申请日：2019-11-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yuna CHOI ,  Changlae Lee ,  Jiyoung Choi ,  Jinwook Jung ,  Keyjo Hong

    IPC: A61B6/00 ,  G06T7/00 ,  A61B6/03

    Abstract: A tomographic image processing apparatus including a display, an input interface configured to receive an external input, a storage storing an input tomographic image of an object, and at least one processor configured to control the display to display the input tomographic image, determine a material combination to be separated from the input tomographic image, and control the display to display material separation information corresponding to the determined material combination for a region of interest selected in the input tomographic image based on the external input. The input tomographic image is a spectral tomographic image having a plurality of tomographic images respectively corresponding to a plurality of energy levels.

    Semiconductor device
    7.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10911034B2

    公开(公告)日：2021-02-02

    申请号：US16679794

    申请日：2019-11-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Woo Seo ,  Youngsoo Shin ,  Jinwook Jung

    IPC: H03K3/3562 ,  H01L27/02 ,  G01R31/317 ,  G01R31/3185 ,  H03K3/037

    Abstract: A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.

    SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20200076410A1

    公开(公告)日：2020-03-05

    申请号：US16679794

    申请日：2019-11-11

    Applicant: Samsung Electronics Co., Ltd. ,  Korea Advanced Institute of Science and Technology

    Inventor： Jae-Woo SEO ,  Youngsoo Shin ,  Jinwook Jung

    IPC: H03K3/3562 ,  G01R31/3185 ,  H01L27/02 ,  G01R31/317

    Abstract: A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.

    Semiconductor device
    9.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US10511293B2

    公开(公告)日：2019-12-17

    申请号：US16103233

    申请日：2018-08-14

    Applicant: Samsung Electronics Co., Ltd. ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

    Inventor： Jae-Woo Seo ,  Youngsoo Shin ,  Jinwook Jung

    IPC: H03K3/3562 ,  H03K3/037 ,  G01R31/317 ,  H01L27/02 ,  G01R31/3185

    Abstract: A semiconductor device may include a clock driver including a first gate line, a second gate line, a third gate line and a fourth gate line each extending in a first direction, the first gate line and the second gate line each configured to receive a clock signal, and the third gate line and the fourth gate line each configured to receive an inverted clock signal; a master latch circuit overlapping the first gate line and the third gate line such that the master latch circuit receive the clock signal from the first gate line and receive the inverted clock signal from the third gate line; and a slave latch circuit overlapping the second gate line and the fourth gate line such that the slave latch circuit receives the clock signal from the second gate line, and receives the inverted clock signal from the fourth gate line.

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