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公开(公告)号:US20240105269A1
公开(公告)日:2024-03-28
申请号:US17954489
申请日:2022-09-28
Applicant: SanDisk Technologies LLC
Inventor: Anirudh Amarnath , Aravind Suresh , Abhijith Prakash
CPC classification number: G11C16/26 , G11C16/102 , G11C16/24
Abstract: Systems and methods for bit line modulation to compensate for cell source variation are disclosed. For example, a method for reading data from non-volatile storage comprising determining a first bit line level based on a first programmed data state that is being sensed and determining a second bit line level based on a second programmed data state that is being sensed. As another example, a storage device comprising a first bit line driver configured to generate a first bit line level for a first set of bit lines corresponding to a first set of memory strings based on a first cell source level associated with the first set of memory strings a second bit line driver configured to generate a second bit line level for a second set of bit lines corresponding to a second set of memory strings based on a second cell source level associated with the second set of memory strings.
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公开(公告)号:US12230333B2
公开(公告)日:2025-02-18
申请号:US17954489
申请日:2022-09-28
Applicant: SanDisk Technologies LLC
Inventor: Anirudh Amarnath , Aravind Suresh , Abhijith Prakash
Abstract: Systems and methods for bit line modulation to compensate for cell source variation are disclosed. For example, a method for reading data from non-volatile storage comprising determining a first bit line level based on a first programmed data state that is being sensed and determining a second bit line level based on a second programmed data state that is being sensed. As another example, a storage device comprising a first bit line driver configured to generate a first bit line level for a first set of bit lines corresponding to a first set of memory strings based on a first cell source level associated with the first set of memory strings a second bit line driver configured to generate a second bit line level for a second set of bit lines corresponding to a second set of memory strings based on a second cell source level associated with the second set of memory strings.
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