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公开(公告)号：US10510383B2
公开(公告)日：2019-12-17
申请号：US15723422
申请日：2017-10-03
发明人： Tai-Yuan Tseng , Anirudh Amarnath
IPC分类号： G11C7/00 , G11C7/12 , G11C16/24 , G11C29/12 , G11C16/34 , G11C16/26 , G11C11/56 , G11C16/08 , G11C16/04
摘要： A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. The selected and unselected sense circuits are configured to perform a state-dependent pre-charge operation during the sense operation. In particular, the selected sense circuits may enable respective pre-charge circuit paths that supply a pre-charge supply voltage to respective sense nodes in the selected sense circuits. Additionally, the unselected sense circuits may disable respective pre-charge circuit paths to prevent the supply of the pre-charge supply voltage to respective sense nodes in the unselected sense circuits. A sense circuit controller may control latches to control the enabling and disabling of the pre-charge circuit paths.
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公开(公告)号：US11869600B2
公开(公告)日：2024-01-09
申请号：US17689188
申请日：2022-03-08
发明人： Jiawei Xu , Anirudh Amarnath , Hiroki Yabe
CPC分类号： G11C16/26 , G11C16/0483 , G11C16/10
摘要： Memory cell sensing by charge sharing between two sense nodes is disclosed. A first sense node and a second sense node are pre-charged and the second node is discharged initiating charge sharing between the first sense node and the second sense node that results in an improved sense margin. Sensing circuitry disclosed herein may include one or more pre-charge circuits, sense enable circuits, and charge-sharing circuits. The increased sense margin achieved by sensing circuitry disclosed herein provides better noise immunity and more accurate sensing results.
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公开(公告)号：US10366729B2
公开(公告)日：2019-07-30
申请号：US15630079
申请日：2017-06-22
发明人： Tai-Yuan Tseng , Anirudh Amarnath
IPC分类号： G11C11/16 , G11C7/08 , G11C7/12 , G11C16/26 , G11C16/04 , G11C16/34 , G11C13/00 , G11C11/56 , G11C16/08 , G11C16/32
摘要： A sense circuit is provided in which the threshold voltage of a memory cell is sensed relative to two different levels using a single control gate voltage on the memory cell. These two levels can be lower and higher verify voltages of a data state in a programming operation, or two read levels of a read operation. A sense node is charged up to a peak level by a pre-charge voltage and by capacitive coupling. The sense node then discharges into the bit line. The sense node voltage is decreased first and second times by capacitive coupling after which first and second bits of data are output based on a level of the sense node. The first and second bits indicate a level of the sense node relative to the lower and higher verify voltages, respectively.
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公开(公告)号：US10121522B1
公开(公告)日：2018-11-06
申请号：US15630089
申请日：2017-06-22
发明人： Tai-Yuan Tseng , Anirudh Amarnath , Yan Li
摘要： A sense circuit is provided in which the threshold voltage of a memory cell is sensed relative to two different levels using a single control gate voltage on the memory cell. These two levels can be higher and lower verify voltages of a data state in a programming operation, or two read levels of a read operation. Two sense nodes which are connected in a cascade configuration such that a first sense node discharges into the bit line initially, and a second sense node may or may not discharge into the bit line, depending on the level to which the first node has discharged. First and second bits of data can be output from the sense circuit based on the levels of the first and second sense nodes to indicate the threshold voltage of the memory cell relative to the higher and lower verify voltages, respectively.
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公开(公告)号：US11521675B1
公开(公告)日：2022-12-06
申请号：US17349009
申请日：2021-06-16
发明人： Kou Tei , Anirudh Amarnath , Ohwon Kwon
IPC分类号： G11C7/00 , G11C11/4096 , G11C5/06 , G11C11/4074 , G11C11/408
摘要： A data storage system includes a storage medium coupled to a storage controller via an electrical interface connected to a plurality of input/output (IO) pads of the storage medium. The storage medium receives a read or write instruction from the storage controller via the IO pads, associates the read or write instruction with memory cells of a first block of a first plane of a plurality of planes of the storage medium, and adjusts a word line voltage level or a source line voltage level for the first block of the first plane based on (i) a position of the first plane with respect to the IO pads of the storage medium and (ii) a position of the first block within the first plane.
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公开(公告)号：US10366739B2
公开(公告)日：2019-07-30
申请号：US15627947
申请日：2017-06-20
发明人： Anirudh Amarnath , Tai-Yuan Tseng
IPC分类号： G11C16/06 , G11C11/4091 , G11C11/4094 , G11C16/26 , G11C7/06 , G11C7/08 , G11C7/12 , G11C11/56 , G11C16/08 , G11C16/24 , G11C16/32 , G11C11/24 , G11C16/04 , G11C16/30
摘要： A circuit includes selected sense circuits configured to be connected to selected bit lines and unselected sense circuits configured to be connected to unselected bit lines during a sense operation. A voltage supply circuit may supply a selected pulse and an unselected pulse to the selected and unselected sense circuits. The selected sense circuits may pass the selected pulse to associated charge-storing circuits, and reject the unselected pulse. The unselected sense circuits may pass the unselected pulse to associated charge-storing circuits, and reject the selected pulse. In addition, voltage-setting circuitry may set sense voltages in the unselected sense circuits to a pre-sense level that matches the pre-sense level of communication voltages in the unselected sense circuits.
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公开(公告)号：US20180197586A1
公开(公告)日：2018-07-12
申请号：US15625848
申请日：2017-06-16
发明人： Qui Nguyen , Alexander Chu , Kenneth Louie , Anirudh Amarnath , Jixin Yu , Yen-Lung Jason Li , Tai-Yuan Tseng , Jong Yuh
IPC分类号： G11C8/08 , G11C5/06 , H01L27/112 , G11C8/10 , G06F13/40
CPC分类号： G11C8/08 , G06F13/4072 , G11C5/06 , G11C8/10 , G11C8/14 , G11C16/08 , H01L27/112 , H01L27/11575 , H01L27/11582
摘要： Apparatuses, systems, and methods are disclosed for three-dimensional non-volatile memory. A stack of word line layers includes word lines for a three-dimensional non-volatile memory array. A stack of word line layers may include a plurality of tiers. Word line switch transistors transfer word line bias voltages to the word lines. Word line contact regions couple word line switch transistors to word lines. A word line contact region includes a stepped structure for a tier of word line layers. A level region separates a word line contact region for a first tier from a word line contact region for a second tier.
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公开(公告)号：US20240105269A1
公开(公告)日：2024-03-28
申请号：US17954489
申请日：2022-09-28
CPC分类号： G11C16/26 , G11C16/102 , G11C16/24
摘要： Systems and methods for bit line modulation to compensate for cell source variation are disclosed. For example, a method for reading data from non-volatile storage comprising determining a first bit line level based on a first programmed data state that is being sensed and determining a second bit line level based on a second programmed data state that is being sensed. As another example, a storage device comprising a first bit line driver configured to generate a first bit line level for a first set of bit lines corresponding to a first set of memory strings based on a first cell source level associated with the first set of memory strings a second bit line driver configured to generate a second bit line level for a second set of bit lines corresponding to a second set of memory strings based on a second cell source level associated with the second set of memory strings.
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公开(公告)号：US11568945B2
公开(公告)日：2023-01-31
申请号：US17343075
申请日：2021-06-09
发明人： Anirudh Amarnath , Jongyeon Kim
IPC分类号： G11C11/34 , G11C16/34 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/04 , G11C11/56 , H01L27/11582 , H01L27/11519 , H01L27/11565 , H01L27/11556
摘要： A method of verifying the programming of a plurality of memory cells in a data storage system includes performing a setup operation including settling of bit lines associated with the subset of memory cells; performing a sensing operation including subjecting the settled bit lines to a verify voltage signal; and performing first and second latching operations identifying memory cells of the subset of memory cells having threshold voltages that meet first and second verify reference voltages, where the first and second latching operations are part of the same program verify operation with no setup time between them.
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公开(公告)号：US20200265899A1
公开(公告)日：2020-08-20
申请号：US16866155
申请日：2020-05-04
发明人： Kenneth Louie , Anirudh Amarnath
摘要： A memory device and associated techniques improve a settling time of bit lines in a memory device during a sensing operation, such as read or verify operation. Supply voltage from power supply terminals in the sense circuits is briefly toggled during a discharge of a selected bit line in response to a voltage on a selected word line being increased to a second word line level or higher. This helps to create an electrical path from the selected bit line through to a supply terminal for discharging the selected bit line such that a settling time of a voltage of the selected bit line is shortened in association with a target memory cell transitioning from a non-conductive state to a conductive state.
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