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公开(公告)号：US20150286524A1
公开(公告)日：2015-10-08
申请号：US14244194
申请日：2014-04-03
Applicant: Seagate Technology LLC
Inventor： Jon David Trantham
CPC classification number: G06F11/108 , G06F11/1004 , G06F11/2289 , G06F12/0246 , G06F2212/1032 , G06F2212/1052 , G06F2212/7207 , G11C29/52
Abstract: Apparatus and method for data integrity management in a data storage device. In accordance with some embodiments, a controller transfers user data blocks between a host device and a main memory. Each user data block has an associated logical address. A data integrity manager generates and stores a verification code for each user data block in a table structure in a local memory. The data integrity manager uses the verification code to independently verify a most current version of a selected user data block is being retrieved by the controller from the main memory during a host read request.
Abstract translation: 数据存储设备中数据完整性管理的装置和方法。 根据一些实施例，控制器在主机设备和主存储器之间传送用户数据块。 每个用户数据块具有相关联的逻辑地址。 数据完整性管理器为本地存储器中的表结构生成并存储每个用户数据块的验证码。 数据完整性管理器使用验证码来独立地验证在主机读取请求期间控制器从主存储器检索所选用户数据块的最新版本。
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公开(公告)号：US10310923B1
公开(公告)日：2019-06-04
申请号：US14471981
申请日：2014-08-28
Applicant: Seagate Technology LLC
Inventor： Jeffrey Vincent DeRosa , Jon David Trantham , Mark Gaertner
IPC: G06F11/07
Abstract: Systems and methods are disclosed for probabilistic aging command sorting, including adjusting an execution order for a command based on a probability of the command reaching a time out threshold. Various example embodiments are directed to selecting a command for execution from a queue of commands awaiting execution, in which the commands have non-uniform attributes influencing their selection and a time limit within which to execute them. In some embodiments, an apparatus may comprise a circuit configured to calculate a first estimated access time to execute a selected command from a command queue, modify the first estimated access time based on a probability of the selected command reaching a time-out age threshold to determine a time out-adjusted access time, and execute the selected command in an order based on the time out-adjusted access time.
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公开(公告)号：US09607632B1
公开(公告)日：2017-03-28
申请号：US15044726
申请日：2016-02-16
Applicant: Seagate Technology LLC
Inventor： Robert Matousek , Thomas Lee Schick , Jon David Trantham
IPC: G11B5/09
CPC classification number: G11B5/09 , G11B5/4886 , G11B20/10027
Abstract: Methods, apparatuses, and systems for allowing a single-die preamp to act as two or more virtual preamps for reading or writing data through multiple heads or elements concurrently. A selection register of a preamplifier is set to enable access to a primary register map. Values of registers in the primary register map are set to program a primary preamp channel for performing read or write operations to a first head. The selection register is then set to enable access to a secondary register map, and values of registers in the secondary register map are set to program a secondary preamp channel for performing read or write operations to a second head. Read or write operations can be performed to the first head through the primary preamp channel at a same time that read or write operations are performed to the second head through the second preamp channel.
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公开(公告)号：US09305596B2
公开(公告)日：2016-04-05
申请号：US14228749
申请日：2014-03-28
Applicant: Seagate Technology LLC
Inventor： Jon David Trantham , William M. Radich , Jason Gadbois , Barmeshwar Vikramaditya
CPC classification number: G11B20/182 , G11B5/09 , G11B5/607 , G11B20/1816 , G11B20/1889 , G11B2005/0021 , G11B2020/1826
Abstract: Apparatus and method for detecting media defects using a multi-sensor transducer. In some embodiments, a first pattern is written to a first track on a rotatable storage media and a second pattern is written to a second track on the media. A first read sensor of a multi-sensor transducer senses the first pattern from the first track and a second read sensor of the multi-sensor transducer concurrently senses the second pattern from the second track. At least one storage media defect is detected responsive to the sensed first and second patterns.
Abstract translation: 使用多传感器传感器检测介质缺陷的装置和方法。 在一些实施例中，将第一图案写入可旋转存储介质上的第一轨道，并将第二图案写入到介质上的第二轨道。 多传感器换能器的第一读取传感器感测来自第一轨道的第一图案，并且多传感器换能器的第二读取传感器同时从第二轨迹感测第二图案。 响应于所感测的第一和第二图案来检测至少一个存储介质缺陷。
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公开(公告)号：US09984719B2
公开(公告)日：2018-05-29
申请号：US14957220
申请日：2015-12-02
Applicant: Seagate Technology LLC
Inventor： Robert Matousek , Todd Lammers , Jon David Trantham
IPC: G11B11/00 , G11B11/105 , G11B7/126 , G11B5/40 , G11B5/455 , G11B19/04 , G11B7/13 , G11B5/31 , G11B7/1267 , G11B7/1263 , G11B5/00
CPC classification number: G11B11/10534 , G11B5/314 , G11B5/40 , G11B5/455 , G11B7/126 , G11B7/1263 , G11B7/1267 , G11B7/13 , G11B11/10595 , G11B19/046 , G11B2005/0021
Abstract: Methods and apparatuses for detecting mode hopping in a laser diode or other optical energy source in heat-assisted magnetic recording. An output power of the laser diode or other optical energy source is measured and the output power is differentiated over time to determine a rate of change. If it is determined that the rate of change exceeds a threshold value, a fault signal is asserted indicating a potential mode hopping event.
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Patent Agency Ranking
6.发明申请DATA MEMORY DEVICE AND CONTROLLER WITH INTERFACE ERROR DETECTION AND HANDLING LOGIC 审中-公开具有接口错误检测和处理逻辑的数据存储器和控制器公开(公告)号：US20170075603A1
公开(公告)日：2017-03-16
申请号：US15272240
申请日：2016-09-21
Applicant: Seagate Technology LLC
Inventor： Jon David Trantham
CPC classification number: G06F3/0619 , G06F3/064 , G06F3/0679 , G06F11/1004 , G06F11/1008 , G06F11/1068 , G11C29/52 , H03M13/09
Abstract: The present disclosure provides a data storage system including a data memory device and controller having interface error detection and handling logic. In one example, a solid-state data memory device is provided and includes a semiconductor package. A memory array is provided in the semiconductor package and an interface is provided that is communicatively couplable to a device bus for receiving data to be stored to the memory array. An error detection component is provided in the semiconductor package and is associated with the interface of the solid-state data memory device. The error detection component is configured to detect errors occurring on data received at the interface prior to the data being stored to the memory array.
Abstract translation: 本公开提供了一种包括具有接口错误检测和处理逻辑的数据存储器件和控制器的数据存储系统。 在一个示例中，提供固态数据存储器件并且包括半导体封装。 在半导体封装中提供存储器阵列，并且提供了可通信地耦合到设备总线的接口，用于接收要存储到存储器阵列的数据。 在半导体封装中提供错误检测部件，并与固态数据存储器件的接口相关联。 错误检测组件被配置为检测在将数据存储到存储器阵列之前在接口处接收的数据上发生的错误。
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公开(公告)号：US09430329B2
公开(公告)日：2016-08-30
申请号：US14244194
申请日：2014-04-03
Applicant: Seagate Technology LLC
Inventor： Jon David Trantham
CPC classification number: G06F11/108 , G06F11/1004 , G06F11/2289 , G06F12/0246 , G06F2212/1032 , G06F2212/1052 , G06F2212/7207 , G11C29/52
Abstract: Apparatus and method for data integrity management in a data storage device. In accordance with some embodiments, a controller transfers user data blocks between a host device and a main memory. Each user data block has an associated logical address. A data integrity manager generates and stores a verification code for each user data block in a table structure in a local memory. The data integrity manager uses the verification code to independently verify a most current version of a selected user data block is being retrieved by the controller from the main memory during a host read request.
Abstract translation: 数据存储设备中数据完整性管理的装置和方法。 根据一些实施例，控制器在主机设备和主存储器之间传送用户数据块。 每个用户数据块具有相关联的逻辑地址。 数据完整性管理器为本地存储器中的表结构生成并存储每个用户数据块的验证码。 数据完整性管理器使用验证码来独立地验证在主机读取请求期间控制器从主存储器检索所选用户数据块的最新版本。
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公开(公告)号：US20180196640A1
公开(公告)日：2018-07-12
申请号：US14328504
申请日：2014-07-10
Applicant: Seagate Technology LLC
Inventor： Bruce Douglas Buch , Jon David Trantham
IPC: G06F7/58
CPC classification number: G06F7/588
Abstract: Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from the generated data.
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公开(公告)号：US10152249B2
公开(公告)日：2018-12-11
申请号：US15272240
申请日：2016-09-21
Applicant: Seagate Technology LLC
Inventor： Jon David Trantham
Abstract: The present disclosure provides a data storage system including a data memory device and controller having interface error detection and handling logic. In one example, a solid-state data memory device is provided and includes a semiconductor package. A memory array is provided in the semiconductor package and an interface is provided that is communicatively couplable to a device bus for receiving data to be stored to the memory array. An error detection component is provided in the semiconductor package and is associated with the interface of the solid-state data memory device. The error detection component is configured to detect errors occurring on data received at the interface prior to the data being stored to the memory array.
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公开(公告)号：US10114614B2
公开(公告)日：2018-10-30
申请号：US14328504
申请日：2014-07-10
Applicant: Seagate Technology LLC
Inventor： Bruce Douglas Buch , Jon David Trantham
IPC: G06F7/58
Abstract: Random numbers are generated using entropic properties associated with circuit hardware. Consistent with one method, a switching voltage regulator circuit is used to generate a random number. Data that is responsive to switching states of the switching voltage regulator circuit is generated. A multi-bit random number is then generated from the generated data.
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