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    Address path architecture
    1.
    发明授权
    Address path architecture 失效
    地址路径架构

    公开(公告)号：US5893932A

    公开(公告)日：1999-04-13

    申请号：US735466

    申请日：1996-10-23

    申请人： Shankar Dey ,  Ming Zhao ,  Dinh Kim Bui

    发明人： Shankar Dey ,  Ming Zhao ,  Dinh Kim Bui

    IPC分类号： G06F13/42 ,  G06F12/00

    CPC分类号： G06F13/4208

    摘要： A microprocessor system integrated on a chip having one or more address generation devices, at least one memory location, and at least one peripheral unit. The address path is divided into two portions having a first logic unit conditioning the address from the one or more address generation devices on the first portion of the address path for gating onto the second portion of the address path. The first logic unit converts a single 16 bit address location into two 8 bit address locations. The first logic unit maintains a first address on the second address path when the CPU is in a next address pipeline mode. A second logic unit selects a memory architecture so that the system can address DRAM units having a various number of rows and/or columns.

    摘要翻译： 集成在具有一个或多个地址产生装置，至少一个存储器位置和至少一个外围单元的芯片上的微处理器系统。 地址路径被划分为具有第一逻辑单元的第二部分，该第一逻辑单元调节来自地址路径的第一部分上的一个或多个地址生成设备的地址，以便选通到地址路径的第二部分。 第一个逻辑单元将单个16位地址位置转换为两个8位地址位置。 当CPU处于下一地址流水线模式时，第一逻辑单元在第二地址路径上保持第一地址。 第二逻辑单元选择存储器架构，使得系统可以寻址具有各种数量的行和/或列的DRAM单元。

    Microprocessor system having multiplexor disposed in first and second read paths between memory CPU and DMA for selecting data from either read path
    2.
    发明授权
    Microprocessor system having multiplexor disposed in first and second read paths between memory CPU and DMA for selecting data from either read path 失效
    具有多路复用器的微处理器系统设置在存储器CPU和DMA之间的第一和第二读取路径中，用于从任一读取路径选择数据

    公开(公告)号：US5862408A

    公开(公告)日：1999-01-19

    申请号：US648523

    申请日：1996-05-13

    申请人： Shankar Dey ,  Dinh Kim Bui ,  Ming Zhao

    发明人： Shankar Dey ,  Dinh Kim Bui ,  Ming Zhao

    IPC分类号： G06F13/40 ,  G06F13/14

    CPC分类号： G06F13/4022

    摘要： A microprocessor system having a first read path from memory and a second read path from peripheral units and an isolation buffer to isolate the first read path from the second read path. The system also has a first write path to memory and a second write path to peripheral units and an isolation buffer to isolate the first write path from the second write path. The isolation buffers also isolate the write paths from the read paths. Also included is a monitoring path between the peripherals and an external bus to allow program monitoring of data in the peripheral units.

    摘要翻译： 具有来自存储器的第一读取路径和来自外围单元的第二读取路径和隔离缓冲器以将第一读取路径与第二读取路径隔离的微处理器系统。 该系统还具有到存储器的第一写入路径和到外围单元的第二写入路径以及隔离缓冲器以将第一写入路径与第二写入路径隔离。 隔离缓冲区还将写入路径与读取路径隔离开来。 还包括外围设备和外部总线之间的监控路径，以便对外围设备中的数据进行程序监控。