公开(公告)号：US07107484B2

公开(公告)日：2006-09-12

申请号：US10614150

申请日：2003-07-08

申请人： Shigeo Yamazaki ,  Shigeyuki Aino

发明人： Shigeo Yamazaki ,  Shigeyuki Aino

IPC分类号： G06F13/00

CPC分类号： G06F11/1691 ,  G06F1/12 ,  G06F11/1044 ,  G06F11/1641 ,  G06F11/165 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/184 ,  G06F12/0815 ,  G06F12/1483 ,  H04L47/10 ,  H04L49/90

摘要： In a lock-step synchronism fault-tolerant computer system including a plurality of computing modules having a processor and a memory in which each computing module processes the same instruction string in synchronization with each other. When detecting disagreement in a state of access to an external bus among the respective processors in each computing module, if no fault is detected in the system including each computing module, processing of resuming operation in synchronization is executed with respect to each computing module after generating an interruption to all the processors to execute delay adjustment for making a state of instruction execution among computing modules be coincident.

摘要翻译： 在包括具有处理器和存储器的多个计算模块的锁步同步容错计算机系统中，每个计算模块在其中彼此同步地处理相同的指令串。 在检测各计算单元的各处理器之间的对外部总线的访问状态的异议时，如果在包含各个计算单元的系统中没有检测到故障，则在生成后对每个计算模块执行同步的恢复操作的处理 所有处理器执行延迟调整以在计算模块之间执行指令状态的中断是一致的。

公开(公告)号：US07418626B2

公开(公告)日：2008-08-26

申请号：US10612929

申请日：2003-07-07

申请人： Shigeyuki Aino ,  Shigeo Yamazaki

发明人： Shigeyuki Aino ,  Shigeo Yamazaki

IPC分类号： G06F11/00

CPC分类号： G06F11/1658 ,  G06F11/1666 ,  G06F11/20

摘要： An information processing apparatus of the present invention includes first and second computer elements which execute the same instructions substantially simultaneously and which are substantially synchronized with each other. The first computer element includes first and second memory elements, which are written by the first and second computer elements, respectively, during a first state. The information processing apparatus has a control element which makes the first computer element read from the second memory element during a second state. Another information processing apparatus has the first and second computer elements, and first and second memory areas which are provided in the first computer element. The first and second memory areas are written by the first computer element and the second computer element, respectively, during a first state. A control element makes the first computer element read from the second memory area during a second state.

摘要翻译： 本发明的信息处理装置包括基本上同时执行相同指令并基本上彼此同步的第一和第二计算机元件。 第一计算机元件包括在第一状态期间分别由第一和第二计算机元件写入的第一和第二存储器元件。 信息处理装置具有使第一计算机元件在第二状态下从第二存储元件读取的控制元件。 另一种信息处理装置具有第一和第二计算机元件以及设置在第一计算机元件中的第一和第二存储区域。 在第一状态期间，分别由第一计算机元件和第二计算机元件写入第一和第二存储器区域。 控制元件使第一计算机元件在第二状态期间从第二存储器区域读取。

公开(公告)号：US07225355B2

公开(公告)日：2007-05-29

申请号：US10614000

申请日：2003-07-08

申请人： Shigeo Yamazaki ,  Shigeyuki Aino

发明人： Shigeo Yamazaki ,  Shigeyuki Aino

IPC分类号： G06F11/00

CPC分类号： G06F11/1687 ,  G06F11/1641 ,  G06F11/1679 ,  G06F11/1683 ,  G06F11/184

摘要： A lock-step synchronism fault-tolerant computer system includes a plurality of computing modules having a processor and a memory in which each computing module processes the same instruction string in synchronization with each other. When disagreement in a state of access to an external bus among the respective processors in each computing module is detected, if no fault is detected in the system including the respective computing modules, an interruption is notified to all of said processors. Synchronization among each computing module is recovered by adjusting timing of a response to an access which each processor executes by an interruption.

摘要翻译： 锁步同步容错计算机系统包括具有处理器和存储器的多个计算模块，其中每个计算模块彼此同步地处理相同的指令串。 当检测到各计算机模块中各个处理器之间访问外部总线状态的不一致时，如果在包括相应的计算模块的系统中没有检测到故障，则向所有所述处理器通知中断。 通过调整每个处理器通过中断执行的访问的响应的定时来恢复每个计算模块之间的同步。

公开(公告)号：US06480940B1

公开(公告)日：2002-11-12

申请号：US09429329

申请日：1999-10-28

申请人： Shigeyuki Aino

发明人： Shigeyuki Aino

IPC分类号： G06F1200

CPC分类号： G06F12/0815

摘要： Cache control protocols can be switched during running without changing an architecture for a segment descriptor or page descriptor for indicating an attribute of an area to be accessed. A plurality of processors each including a cache memory constitute a multiprocessor system which shares a main memory via a system bus. Each processor has module detecting means for detecting execution of a module which accesses a shared memory area on the main memory, by comparing the virtual space number and the instruction segment number concerning the accessing module with those numbers concerning the software modules preset which may access the shared memory area. Memory access executed in a module detected by the module detecting means is controlled in a cache control protocol of a store-through scheme which updates a main memory simultaneously with update of a cache memory. Memory access executed in other modules is controlled in a cache control protocol of a store-in scheme which does not update a main memory at update of a cache memory.

摘要翻译： 可以在运行期间切换缓存控制协议，而不改变用于指示要访问的区域的属性的段描述符或页描述符的架构。 每个包括高速缓存存储器的多个处理器构成通过系统总线共享主存储器的多处理器系统。 每个处理器具有用于检测访问主存储器上的共享存储区域的模块的执行的模块检测装置，通过将有关访问模块的虚拟空间编号和指令段编号与预先设定的软件模块的那些数字进行比较，这些编号可以访问 共享内存区域。 在由模块检测装置检测到的模块中执行的存储器访问被控制在通过更新主存储器的存储直接方案的高速缓存控制协议中，同时更新高速缓冲存储器。 在其他模块中执行的存储器访问在高速缓存存储器的更新时不更新主存储器的存储方案的高速缓存控制协议中被控制。