公开(公告)号：US20190034301A1

公开(公告)日：2019-01-31

申请号：US15665343

申请日：2017-07-31

申请人： Oracle International Corporation

发明人： Christopher West ,  James Baer

IPC分类号： G06F11/20 ,  G06F9/38

CPC分类号： G06F11/2035 ,  G06F9/3861 ,  G06F9/3877 ,  G06F11/1658 ,  G06F11/1687 ,  G06F11/184 ,  G06F2201/85

摘要： Techniques for system recovery using a failover processor are disclosed. A first processor, with a first instruction set, is configured to execute operations of a first type; and a second processor, with a second instruction set different from the first instruction set, is configured to execute operations of a second type. A determination is made that the second processor has failed to execute at least one operation of the second type within a particular period of time. Responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time, the first processor is configured to execute both the operations of the first type and the operations of the second type.

公开(公告)号：US09507645B2

公开(公告)日：2016-11-29

申请号：US14057281

申请日：2013-10-18

申请人： FUJITSU LIMITED

发明人： Hiromasa Yamauchi ,  Koichiro Yamashita ,  Takahisa Suzuki ,  Koji Kurihara ,  Toshiya Otomo ,  Naoki Odate

IPC分类号： G06F9/46 ,  G06F12/00 ,  G06F9/52 ,  G06F9/50 ,  G06F9/38 ,  G06F12/08 ,  G06F11/16

CPC分类号： G06F9/52 ,  G06F9/3851 ,  G06F9/5027 ,  G06F11/1687 ,  G06F11/1695 ,  G06F12/0811 ,  G06F12/0842

摘要： A thread processing method that is executed by a multi-core processor, includes supplying a command to execute a first thread to a first processor; judging a dependence relationship between the first thread and a second thread to be executed by a second processor; comparing a first threshold and a frequency of access of any one among shared memory and shared cache memory by the first thread; and changing a phase of a first operation clock of the first processor when the access frequency is greater than the first threshold and upon judging that no dependence relationship exists.

摘要翻译： 一种由多核处理器执行的线程处理方法，包括向第一处理器提供执行第一线程的命令; 判断由第二处理器执行的第一线程和第二线程之间的依赖关系; 通过第一线程比较共享存储器和共享高速缓冲存储器中的任何一个的第一阈值和访问频率; 以及当所述访问频率大于所述第一阈值时，并且在判断出不存在依赖关系时，改变所述第一处理器的第一操作时钟的相位。

公开(公告)号：US09400666B2

公开(公告)日：2016-07-26

申请号：US14029181

申请日：2013-09-17

申请人： YOKOGAWA ELECTRIC CORPORATION

发明人： Yoshitaka Yoshida ,  Shota Uehara ,  Takeshi Ohno

IPC分类号： G06F11/16 ,  G06F9/455 ,  G06F11/14 ,  G06F11/34 ,  G06F11/20

CPC分类号： G06F9/45533 ,  G06F11/1484 ,  G06F11/1683 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/2038 ,  G06F11/2097 ,  G06F11/3409

摘要： A fault tolerant system includes a primary virtual machine that is formed on a primary machine in which a primary hypervisor runs, and is configured to input virtual interrupt based on an external interrupt from the primary hypervisor to a primary guest OS, and a secondary virtual machine that is formed on a secondary machine in which a secondary hypervisor runs, and is configured to input the virtual interrupt to a secondary guest OS on the basis of timing information on the virtual interrupt transmitted from the primary virtual machine. The primary virtual machine is configured to transmit the timing information on the virtual interrupt including the number of branch instructions executed by the primary guest OS before inputting the virtual interrupt, and including an execution suspension position when inputting the virtual interrupt to the secondary virtual machine.

摘要翻译： 容错系统包括形成在主虚拟机管理程序运行的主机上的主虚拟机，并且被配置为基于来自主虚拟机管理程序的外部中断将主要虚拟中断输入到主客户机OS，以及次虚拟机 其形成在二级管理程序运行的辅助计算机上，并且被配置为基于从主虚拟机发送的虚拟中断的定时信息将虚拟中断输入到辅助客户机OS。 主虚拟机被配置为在虚拟中断之前发送包括由主客户OS执行的分支指令的数量的虚拟中断的定时信息，并且在向虚拟中断输入虚拟中断时包括执行暂停位置。

公开(公告)号：US20140373028A1

公开(公告)日：2014-12-18

申请号：US13920524

申请日：2013-06-18

申请人： Advanced Micro Devices, Inc.

发明人： Alexander Lyashevsky ,  Sudhanva Gurumurthi ,  Vilas Sridharan

IPC分类号： G06F9/52

CPC分类号： G06F11/00 ,  G06F9/3851 ,  G06F9/52 ,  G06F11/1608 ,  G06F11/1633 ,  G06F11/1637 ,  G06F11/1654 ,  G06F11/1687 ,  G06F11/202 ,  G06F11/2038 ,  G06F11/2041 ,  G06F11/2048 ,  G06F2201/825 ,  G06F2201/83

摘要： A system, method and computer program product to execute a first and a second work-group, and compare the signature variables of the first work-group to the signature variables of the second work-group via a synchronization mechanism. The first and the second work-group are mapped to an identifier via software. This mapping ensures that the first and second work-groups execute exactly the same data for exactly the same code without changes to the underlying hardware. By executing the first and second work-groups independently, the underlying computation of the first and second work-groups can be verified. Moreover, system performance is not substantially affected because the execution results of the first and second work-groups are compared only at specified comparison points.

摘要翻译： 一种用于执行第一和第二工作组的系统，方法和计算机程序产品，并且经由同步机制将第一工作组的签名变量与第二工作组的签名变量进行比较。 第一个和第二个工作组通过软件映射到一个标识符。 此映射确保第一个和第二个工作组对完全相同的代码执行完全相同的数据，而不会更改底层硬件。 通过独立地执行第一和第二工作组，可以验证第一和第二工作组的基础计算。 此外，由于第一和第二工作组的执行结果仅在指定的比较点进行比较，系统性能基本上不受影响。

公开(公告)号：US20140082408A1

公开(公告)日：2014-03-20

申请号：US14029075

申请日：2013-09-17

申请人： YOKOGAWA ELECTRIC CORPORATION

发明人： Yoshitaka YOSHIDA ,  Shota UEHARA ,  Takeshi OHNO

IPC分类号： G06F11/14

CPC分类号： G06F11/1415 ,  G06F11/1484 ,  G06F11/1687 ,  G06F11/1691 ,  G06F11/2038 ,  G06F11/2097

摘要： A primary virtual machine is formed on a primary machine in which a primary hypervisor runs, and inputs virtual interrupt based on an external interrupt from the primary hypervisor to a primary guest OS. A secondary virtual machine is formed on a secondary machine in which a secondary hypervisor runs, and inputs the virtual interrupt to a secondary guest OS on the basis of timing information on the virtual interrupt transmitted from the primary virtual machine. When inputting the virtual interrupt to the primary guest OS, the primary virtual machine suspends the primary guest OS, and determines whether the suspended position is in a critical section. If the suspended position is not in the critical section, the primary virtual machine inputs the virtual interrupt at the suspended position. If the suspended position is in the critical section, the primary virtual machine changes the suspended position, and again performs the determination.

摘要翻译： 在主虚拟机管理程序运行的主计算机上形成主虚拟机，并且基于从主管理程序到主客户操作系统的外部中断输入虚拟中断。 二级虚拟机形成在辅助机器上，次级虚拟机管理程序运行，并且根据从主虚拟机发送的虚拟中断的定时信息将虚拟中断输入到辅助客户机OS。 当虚拟中断向主客户机操作系统输入时，主虚拟机将挂起主客机操作系统，并确定暂停的位置是否在临界区。 如果暂停位置不在关键部分，则主虚拟机将虚拟中断输入到挂起位置。 如果暂停位置处于临界区，则主虚拟机将更改挂起位置，并再次执行确定。

公开(公告)号：US20140032860A1

公开(公告)日：2014-01-30

申请号：US14110786

申请日：2011-04-21

申请人： Hiromichi Yamada ,  Nobuyasu Kanekawa ,  Teruaki Sakata ,  Kesami Hagiwara ,  Yuichi Ishiguro

发明人： Hiromichi Yamada ,  Nobuyasu Kanekawa ,  Teruaki Sakata ,  Kesami Hagiwara ,  Yuichi Ishiguro

IPC分类号： G06F12/02

CPC分类号： G06F12/02 ,  G06F11/1641 ,  G06F11/167 ,  G06F11/1687 ,  G06F2201/845

摘要： First data to be written which is output from a function module (2) is supplied to a built-in memory (3) and a first buffer memory (11), and second data to be written which is output from the function module (2) is supplied to the built-in memory (3) and a second buffer memory (12). The first and second FIFO memories (13, 14) select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (11, 12), and do not select other data items. A comparator (15) compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories (13, 14) with each other.

摘要翻译： 从功能模块（2）输出的要写入的第一数据被提供给内置存储器（3）和第一缓冲存储器（11），以及从功能模块（2）输出的要写入的第二数据 ）被提供给内置存储器（3）和第二缓冲存储器（12）。 第一和第二FIFO存储器（13,14）从从第一和第二缓冲存储器（11,12）顺次输出的多个第一和第二输出数据项中选择并存储具有预定数量的输出的数据项，以及 不要选择其他数据项。 比较器（15）将由第一和第二FIFO存储器（13,14）输出的具有预定数量的输出的数据项彼此进行比较。

公开(公告)号：US20130275626A1

公开(公告)日：2013-10-17

申请号：US13881044

申请日：2010-10-25

申请人： Sungho Kim ,  Eiji Nishijima

发明人： Sungho Kim ,  Eiji Nishijima

IPC分类号： H04L12/24

CPC分类号： H04L41/50 ,  G06F9/52 ,  G06F11/1675 ,  G06F11/1687 ,  G06F11/182 ,  G06F11/184

摘要： A computer system includes a plurality of computer nodes, each including an external communications unit. An application unit executes processing in accordance with a processing request. A synchronization unit establishes synchronization of the processing between each computer node and other computer nodes. The processing is executed by each computer node, and an inter-node communications unit executes transmission/reception of information between each computer node and the other computer nodes. The synchronization unit transmits the processing request to the other computer nodes via the inter-node communications unit, the processing request being received by the external communications unit. Also, the synchronization unit receives processing requests from the other computer nodes as well via the inter-node communications unit. Based on the number of the computer nodes that have received the same processing request via the external communications units, the synchronization unit selects a processing request that should be executed by the application unit.

摘要翻译： 计算机系统包括多个计算机节点，每个计算机节点包括外部通信单元。 应用单元根据处理请求执行处理。 同步单元建立每个计算机节点与其他计算机节点之间的处理的同步。 处理由每个计算机节点执行，并且节点间通信单元执行每个计算机节点与其他计算机节点之间的信息的发送/接收。 同步单元经由节点间通信单元向其他计算机节点发送处理请求，处理请求由外部通信单元接收。 此外，同步单元也经由节点间通信单元接收来自其他计算机节点的处理请求。 基于经由外部通信单元接收到相同处理请求的计算机节点的数量，同步单元选择应由应用单元执行的处理请求。

公开(公告)号：US20130232383A1

公开(公告)日：2013-09-05

申请号：US13856485

申请日：2013-04-04

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Hiromichi YAMADA ,  Kotaro SHIMAMURA ,  Kesami HAGIWARA ,  Yoshikazu KIYOSHIGE ,  Yuichi ISHIGURO

IPC分类号： G06F11/16

CPC分类号： G06F11/1608 ,  G06F11/004 ,  G06F11/1641 ,  G06F11/1687 ,  G06F2201/83 ,  G06F2201/845

摘要： A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors. Moreover, since the comparison of the comparator is enabled when comparison enable is given from all the CPUs, the comparison operation result can be obtained based on the timing at which the results of compression by the plurality of compressors are determined.

摘要翻译： 一种微控制器，其能够通过由多个CPU执行不同的程序来提高处理性能，并且能够通过评估由多个CPU执行的相同处理的结果来检测用于安全需要的处理的异常。 提供了包括CPU和存储器在内的多个处理系统，每个处理系统中的CPU输出的数据分别由用于每个CPU的压缩机压缩和存储。 压缩存储数据由比较器相互比较，当比较结果表示不匹配时，可以检测出异常处理。 即使当多个CPU异步地执行相同的处理时，获得相同处理结果的定时也是不同的，因此可以容易地将它们的处理结果彼此进行比较，因为压缩是由压缩器执行的。 此外，由于在从所有CPU给出比较使能时能够进行比较器的比较，所以可以基于确定多个压缩机的压缩结果的定时来获得比较运算结果。

公开(公告)号：US08281304B2

公开(公告)日：2012-10-02

申请号：US12233461

申请日：2008-09-18

申请人： Tetsuro Kimura

发明人： Tetsuro Kimura

IPC分类号： G06F9/455 ,  G06F9/46

CPC分类号： G06F11/1687 ,  G06F9/45533 ,  G06F9/52 ,  G06F11/1683 ,  G06F11/1691 ,  G06F11/2038 ,  G06F11/2048 ,  G06F11/2097

摘要： A high availability system includes a first computer on which a first virtual computer and a first hypervisor managing the first virtual computer operate, and a second computer on which a second virtual computer and a second hypervisor managing the second virtual computer operate. The first hypervisor includes an acquisition unit which acquires synchronization information associated with an event, wherein the event has occurred in the first virtual computer and accompanies an input to the first virtual computer, and a transmission unit which transmits the acquired synchronization information to the second hypervisor. The second hypervisor includes a reception unit which receives the synchronization information from the first hypervisor, and a control unit which performs control to match an input to the second virtual computer with an input to the first virtual computer in accordance with the received synchronization information.

摘要翻译： 高可用性系统包括第一计算机，第一虚拟计算机和管理第一虚拟计算机的第一管理程序在其上运行;第二计算机，其上管理第二虚拟计算机的第二虚拟计算机和第二管理程序在其上运行。 第一管理程序包括获取单元，其获取与事件相关联的同步信息，其中所述事件已经在所述第一虚拟计算机中发生并且伴随着到所述第一虚拟计算机的输入，以及发送单元，其将所获取的同步信息发送到所述第二管理程序 。 第二管理程序包括接收来自第一管理程序的同步信息的接收单元，以及控制单元，其根据接收的同步信息执行将输入与第二虚拟计算机的输入与第一虚拟计算机的输入进行匹配。

公开(公告)号：US08156371B2

公开(公告)日：2012-04-10

申请号：US12485581

申请日：2009-06-16

申请人： Brett D. Oliver ,  Joseph Caltagirone ,  Christopher Brickner

发明人： Brett D. Oliver ,  Joseph Caltagirone ,  Christopher Brickner

IPC分类号： G06F11/00

CPC分类号： G06F11/1687 ,  G06F11/1637

摘要： An apparatus comprises first and second modules configured to operate in a lockstep mode and a reset mode. Each of the first and second modules is configured to asynchronously enter the reset mode when a parent reset signal is asserted at the respective each module. Each of the first and second modules is configured to, in response to the asserted parent reset signal being negated at the respective each module, indicate to the respective other module that the respective each module is ready to exit the reset mode and exit the reset mode when the respective other module has also indicated that the respective other module is ready to exit the reset mode.

摘要翻译： 一种装置包括配置成在锁步模式和复位模式下操作的第一和第二模块。 当在相应的每个模块断言父复位信号时，第一和第二模块中的每一个被配置为异步地进入复位模式。 第一和第二模块中的每一个被配置为响应于相应的每个模块处的被断言的母线复位信号被否定，向相应的另一个模块指示相应的每个模块准备退出复位模式并退出复位模式 当相应的其他模块还指示相应的另一模块准备退出复位模式时。