公开(公告)号：US20240120936A1

公开(公告)日：2024-04-11

申请号：US18473823

申请日：2023-09-25

Applicant: Socionext Inc.

Inventor： Hidetaka HANEDA

IPC: H03M1/46

CPC classification number: H03M1/462 ,  H03M1/466

Abstract: In an AD converter circuit, a comparison circuit includes: a differential comparison circuit configured to perform comparison determination of differential input signals based on an internal clock signal and generate first differential output signals indicating a determination result; a determination assist circuit configured to receive the first differential output signals and generate second differential output signals; a latch circuit configured to hold the second differential output signals and generate third differential output signals; and a clock generation circuit configured to generate the internal clock signal based on the third differential output signals. The determination assist circuit varies a value of the first differential output signals and generate the second differential output signals when a designed time has elapsed with values of the first differential output signals being unvaried from a reset value since the start of an operation of the comparison determination in the differential comparison circuit.

公开(公告)号：US20230261663A1

公开(公告)日：2023-08-17

申请号：US18102454

申请日：2023-01-27

Applicant: Socionext Inc.

Inventor： Shota HINO ,  Hidetaka HANEDA

IPC: H03M1/06

CPC classification number: H03M1/0604

Abstract: An analog-to-digital converter circuit includes: a reference voltage node configured to be supplied with a reference voltage; an analog-to-digital converter circuit unit including a reference voltage input node configured to be electrically connected to the reference voltage node, the reference voltage being input to the reference voltage input node, the analog-to-digital converter circuit unit configured to convert an input analog voltage into a digital value based on the reference voltage; a voltage generation circuit configured to be electrically connected to the reference voltage node and generate an internal operating voltage based on the reference voltage; and a charge compensation circuit configured to operate based on the internal operating voltage, and during operation of the analog-to-digital converter circuit unit, the charge compensation circuit configured to compensate the reference voltage input node for charge.