公开(公告)号：US20230261664A1

公开(公告)日：2023-08-17

申请号：US18301708

申请日：2023-04-17

Applicant: Socionext Inc.

Inventor： Kenta ARUGA ,  Takeshi TAKAYAMA ,  Shota HINO

IPC: H03M1/12 ,  H03M1/46

CPC classification number: H03M1/1245 ,  H03M1/462

Abstract: A sampling circuit includes: a first capacitor including a first terminal and a second terminal; a second capacitor including a third terminal and a fourth terminal; a first input node configured to receive a first input voltage that is one of a differential input voltage; a second input node configured to receive a second input voltage that is the other of the differential input voltage; a first switch circuit configured to be provided between the first input node and the first terminal; a second switch circuit configured to be provided between the second input node and the third terminal; a third switch circuit configured to be provided between the first terminal and the third terminal; and a fourth switch circuit configured to be provided between the second terminal and the fourth terminal.

公开(公告)号：US20230261663A1

公开(公告)日：2023-08-17

申请号：US18102454

申请日：2023-01-27

Applicant: Socionext Inc.

Inventor： Shota HINO ,  Hidetaka HANEDA

IPC: H03M1/06

CPC classification number: H03M1/0604

Abstract: An analog-to-digital converter circuit includes: a reference voltage node configured to be supplied with a reference voltage; an analog-to-digital converter circuit unit including a reference voltage input node configured to be electrically connected to the reference voltage node, the reference voltage being input to the reference voltage input node, the analog-to-digital converter circuit unit configured to convert an input analog voltage into a digital value based on the reference voltage; a voltage generation circuit configured to be electrically connected to the reference voltage node and generate an internal operating voltage based on the reference voltage; and a charge compensation circuit configured to operate based on the internal operating voltage, and during operation of the analog-to-digital converter circuit unit, the charge compensation circuit configured to compensate the reference voltage input node for charge.