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    CHIP TO CHIP TIME SYNCHRONIZATION
    1.
    发明公开
    CHIP TO CHIP TIME SYNCHRONIZATION 审中-公开

    公开(公告)号：US20230403130A1

    公开(公告)日：2023-12-14

    申请号：US18208754

    申请日：2023-06-12

    Applicant: Space Exploration Technologies Corp.

    Inventor： Andras Tantos ,  David Francois Jacquet ,  Mario Toma

    IPC: H04L7/033

    CPC classification number: H04L7/0331

    Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a first reference clock signal and generate a first reference time signal based on the timing signal and the first reference clock signal. The IC chip is configured to generate a second reference time signal based on the first reference time signal and a second reference clock signal, different from the first reference clock signal The second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal. The IC chip is configured to synchronize one or more actions performed by the IC chip based on one or more of the first reference time signal or the second reference time signal.

    OVER-THE-AIR CALIBRATION OF ANTENNA SYSTEM
    3.
    发明申请
    OVER-THE-AIR CALIBRATION OF ANTENNA SYSTEM 有权

    公开(公告)号：US20220278760A1

    公开(公告)日：2022-09-01

    申请号：US17747895

    申请日：2022-05-18

    Applicant: Space Exploration Technologies Corp.

    Inventor： David Francois Jacquet ,  Masoud Kahrizi ,  Robert Baummer, JR. ,  Jean-Noel Rozec ,  Fabrice Jean André Belvèze ,  Paul Lee Pearson ,  Francois Lucien Emile Icher ,  Marc Gens ,  Pascal Triaire

    IPC: H04B17/11 ,  H04B1/38

    Abstract: In an embodiment, an apparatus includes a transmit section including a first baseband section and a first radio frequency (RF) section, wherein the transmit section is configured to receive a calibration signal, the first RF section is configured to generate a RF calibration signal based on modulating the calibration signal. The calibration signal comprises an orthogonal code based signal; and a receive section configured to receive the RF calibration signal over-the-air, the receive section includes a second RF section and a calibration section, the second RF section is configured to generate a received calibration signal based on the RF calibration signal, the received calibration signal and a reference signal associated with the RF calibration signal comprise inputs to the calibration section and the calibration section is configured to determine one or more of gain, baseband delay, or RF delay compensation values, based on the inputs, to calibrate the transmit section.

    PHASE LOCK LOOP (PLL) SYNCHRONIZATION
    4.
    发明申请
    PHASE LOCK LOOP (PLL) SYNCHRONIZATION 有权

    公开(公告)号：US20210376837A1

    公开(公告)日：2021-12-02

    申请号：US17401208

    申请日：2021-08-12

    Applicant: Space Exploration Technologies Corp.

    Inventor： David Francois Jacquet ,  Mostafa Ghazali ,  Masoud Kahrizi ,  Andras Tantos

    IPC: H03L7/07 ,  H03L7/197

    Abstract: In an embodiment, an apparatus includes a first integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal; and a second IC chip configured to receive the timing signal and the reference clock signal. The first and second IC chips are configured to generate respective first and second reference time signals based on the timing signal and the reference clock signal. The first and second IC chips include a respective first phase lock loop (PLL) and second PLL. The first PLL and the second PLL are synchronized to each other based on the first reference time signal and the second reference time signal.

    Chip to chip time synchronization
    5.
    发明授权
    Chip to chip time synchronization 有权

    公开(公告)号：US12184752B2

    公开(公告)日：2024-12-31

    申请号：US18208754

    申请日：2023-06-12

    Applicant: Space Exploration Technologies Corp.

    Inventor： Andras Tantos ,  David Francois Jacquet ,  Mario Toma

    IPC: H04L7/033

    Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a first reference clock signal and generate a first reference time signal based on the timing signal and the first reference clock signal. The IC chip is configured to generate a second reference time signal based on the first reference time signal and a second reference clock signal, different from the first reference clock signal The second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal. The IC chip is configured to synchronize one or more actions performed by the IC chip based on one or more of the first reference time signal or the second reference time signal.

    Chip to chip time synchronization
    6.
    发明授权
    Chip to chip time synchronization 有权

    公开(公告)号：US11677538B2

    公开(公告)日：2023-06-13

    申请号：US17478599

    申请日：2021-09-17

    Applicant: Space Exploration Technologies Corp.

    Inventor： Andras Tantos ,  David Francois Jacquet ,  Mario Toma

    IPC: H04L7/033

    CPC classification number: H04L7/0331

    Abstract: In an embodiment, an apparatus includes an integrated circuit (IC) chip configured to receive a timing signal and a reference clock signal and generate a first reference time signal based on the timing signal and the reference clock signal. The IC chip includes a clock phase lock loop (PLL) configured to generate and provide a second reference clock signal at a higher frequency than the reference clock signal; the IC chip is further configured to generate a second reference time signal based on the first reference time signal and the second reference clock signal. The second reference time signal specifies a count of a number of cycles of the second reference clock signal starting from a particular cycle of the second reference clock signal. The second reference time signal has a finer count resolution than the first reference time signal for a same time period.

    NEAR ZERO INTERMEDIATE FREQUENCY (NZIF) COMPENSATION OF LOCAL OSCILLATOR LEAKAGE
    9.
    发明申请
    NEAR ZERO INTERMEDIATE FREQUENCY (NZIF) COMPENSATION OF LOCAL OSCILLATOR LEAKAGE 有权

    公开(公告)号：US20220368014A1

    公开(公告)日：2022-11-17

    申请号：US17872964

    申请日：2022-07-25

    Applicant: Space Exploration Technologies Corp.

    Inventor： David Francois Jacquet ,  Marc Gens ,  Paul Lee Pearson ,  Pascal Triaire

    IPC: H01Q3/26 ,  H04B17/19 ,  H01Q3/42 ,  H04B1/00 ,  H04B17/12 ,  H01Q3/38

    Abstract: In an embodiment, a communications system includes a first transmitter including a digital beamforming baseband section configured to receive an input signal to be transmitted, the input signal at a baseband frequency, and a modulation section electrically coupled to the digital beamforming baseband section and a first antenna of a phased array antenna. The modulation section is configured to receive a local oscillator signal at a first local oscillator frequency and apply a baseband frequency shift to the input signal to generate a baseband frequency shifted input signal. The modulation section generates a modulated signal based on the input signal. The communication system includes a second transmitter included in a second IC chip of the plurality of IC chips electrically coupled to a second antenna and configured to provide a second modulated signal at the carrier frequency and a second LO leakage signal at a second local oscillator frequency.

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