利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.043 秒)

    INTEGRATED FIREWALL, IPS, AND VIRUS SCANNER SYSTEM AND METHOD
    3.
    发明申请
    INTEGRATED FIREWALL, IPS, AND VIRUS SCANNER SYSTEM AND METHOD 有权
    综合防火墙，IPS和病毒扫描仪系统及方法

    公开(公告)号：US20110296516A1

    公开(公告)日：2011-12-01

    申请号：US13205444

    申请日：2011-08-08

    申请人： Steven M. Haeffele ,  Ramesh M. Gupta ,  Ananth Raman ,  Srikant Vissamsetti

    发明人： Steven M. Haeffele ,  Ramesh M. Gupta ,  Ananth Raman ,  Srikant Vissamsetti

    IPC分类号： G06F17/00

    CPC分类号： H04L63/0218 ,  H04L63/0227 ,  H04L63/1408 ,  H04L63/1441 ,  H04L63/20

    摘要： A system, method and computer program product are provided including a router and a security sub-system coupled to the router. Such security sub-system includes a plurality of virtual firewalls, a plurality of virtual intrusion prevention systems (IPSs), and a plurality of virtual virus scanners. Further, each of the virtual firewalls, IPSs, and virus scanners is assigned to at least one of a plurality of user and is configured in a user-specific.

    摘要翻译： 提供了一种系统，方法和计算机程序产品，其包括路由器和耦合到路由器的安全子系统。 这种安全子系统包括多个虚拟防火墙，多个虚拟入侵防御系统（IPS）以及多个虚拟病毒扫描器。 此外，每个虚拟防火墙，IPS和病毒扫描器被分配给多个用户中的至少一个，并且被配置为用户特定的。

    Digital data processing system having an I/O means using unique address providing and access priority control techniques
    7.
    发明授权
    Digital data processing system having an I/O means using unique address providing and access priority control techniques 失效
    具有使用独特地址提供和访问优先级控制技术的I / O装置的数字数据处理系统

    公开(公告)号：US4455602A

    公开(公告)日：1984-06-19

    申请号：US266402

    申请日：1981-05-22

    申请人： Ward Baxter, III ,  William N. Coder ,  Steven M. Haeffele

    发明人： Ward Baxter, III ,  William N. Coder ,  Steven M. Haeffele

    IPC分类号： G06F9/35 ,  G06F13/18 ,  G06F3/00

    CPC分类号： G06F13/18 ,  G06F9/35

    摘要： A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique indentification of information as objects and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration. Information is identified to bit granular level and to information type and format. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.

    摘要翻译： 具有灵活的内部结构的数据处理系统，具有多层次的控制和堆栈机制以及执行多个并发操作的能力，并向用户提供灵活的简化界面，保护用户不受任何用户的影响。 该系统内部由多个独立的独立处理器组成，每个独立的处理器具有单独的微指令控制和至少一个独立于中央通信和存储器节点的独立端口。 通信和存储器节点是具有独立且独立的微指令控制的独立处理器，并且包括能够执行多个并发存储器和通信操作的多个独立操作的微指令控制的处理器。 寻址机制允许作为对象的信息的永久唯一标识，以及所有这样的系统可访问和共同的极大的地址空间。 地址与系统物理配置无关。 信息被识别为细粒度级别和信息类型和格式。 保护机制提供与个体信息相关联的可变访问权限。 用户语言指令被转换为方言编码的，统一的中间级指令，以便为所有用户语言提供相同的执行功能。 操作数由统一格式名称引用，通过对用户透明的内部机制转换为地址。

    Digital data processing system
    8.
    发明授权
    Digital data processing system 失效
    数字数据处理系统

    公开(公告)号：US4493024A

    公开(公告)日：1985-01-08

    申请号：US266406

    申请日：1981-05-22

    申请人： Ward Baxter, II ,  Gerald F. Clancy ,  Ronald H. Gruner ,  Craig J. Mundie ,  Brett L. Bachman ,  Stephen R. Redfield ,  William N. Coder ,  Thomas M. Jones ,  David L. Houseman ,  Charles J. Young ,  Steven M. Haeffele

    发明人： Ward Baxter, II ,  Gerald F. Clancy ,  Ronald H. Gruner ,  Craig J. Mundie ,  Brett L. Bachman ,  Stephen R. Redfield ,  William N. Coder ,  Thomas M. Jones ,  David L. Houseman ,  Charles J. Young ,  Steven M. Haeffele

    IPC分类号： G06F9/318 ,  G06F9/35 ,  G06F13/00

    CPC分类号： G06F9/30192 ,  G06F9/35

    摘要： A data processing system having a flexible internal structure, protected from and effecitvely invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate, independent processors, each having a separate microinstruction control and at least one separate, independent port to a central communications and memory node. The communications and memory node is an independent processor having separate, independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent, unique identification of information and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration. Information is identified to bit granular level and to information type and format. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform, intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.

    摘要翻译： 具有灵活的内部结构的数据处理系统，具有多层次的控制和堆栈机制以及执行多个并发操作的能力，并为用户提供灵活，简化的界面，保护用户不受任何用户无害的影响。 该系统内部由多个独立的独立处理器组成，每个独立的处理器具有单独的微指令控制和至少一个独立于中央通信和存储器节点的独立端口。 通信和存储器节点是具有独立且独立的微指令控制的独立处理器，并且包括能够执行多个并发存储器和通信操作的多个独立操作的微指令控制的处理器。 寻址机制允许永久，唯一的信息识别和所有这些系统可访问和共同的极大的地址空间。 地址与系统物理配置无关。 信息被识别为细粒度级别和信息类型和格式。 保护机制提供与个体信息相关联的可变访问权限。 用户语言指令被转换为方言编码的，统一的中间级指令，以便为所有用户语言提供相同的执行功能。 操作数由统一格式名称引用，通过对用户透明的内部机制转换为地址。