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公开(公告)号：US20240320009A1
公开(公告)日：2024-09-26
申请号：US18577220
申请日：2022-04-29
发明人： Jun ZHANG , Xinghui LI
CPC分类号： G06F9/3853 , G06F9/3004 , G06F9/35
摘要： Provided in the present disclosure are a data access method and apparatus, and a non-transient computer-readable storage medium. The method includes: acquiring a plurality of instructions to be processed, wherein each of the instructions to be processed includes an address to be accessed; determining instructions to be merged from among the plurality of instructions to be processed, and performing merging processing on the instructions to be merged, so as to obtain a merged instruction; and performing data access according to an address to be accessed corresponding to the merged instruction.
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公开(公告)号：US20240211413A1
公开(公告)日：2024-06-27
申请号：US18596835
申请日：2024-03-06
申请人： Google LLC
CPC分类号： G06F13/161 , G06F9/35 , G06F9/3869 , G06F9/522
摘要： Generally disclosed herein is a hardware/software interface for asynchronous data movement between an off-core memory and a core-local memory, referred to as “stream transfers”, and a stream ordering model. The stream transfers allow software to more efficiently express common data-movement patterns, specifically ones seen in sparse workloads. Direct stream instructions that belong to a stream are processed in-order. For indirect stream instructions, offset elements in an offset list are processed in order. A sync flag is updated to indicate monotonic incremental progress for the stream.
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公开(公告)号：US11977499B2
公开(公告)日：2024-05-07
申请号：US17722782
申请日：2022-04-18
申请人： Google LLC
CPC分类号： G06F13/161 , G06F9/35 , G06F9/3869 , G06F9/522
摘要： Generally disclosed herein is a hardware/software interface for asynchronous data movement between an off-core memory and a core-local memory, referred to as “stream transfers”, and a stream ordering model. The stream transfers allow software to more efficiently express common data-movement patterns, specifically ones seen in sparse workloads. Direct stream instructions that belong to a stream are processed in-order. For indirect stream instructions, offset elements in an offset list are processed in order. A sync flag is updated to indicate monotonic incremental progress for the stream.
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公开(公告)号：US11681531B2
公开(公告)日：2023-06-20
申请号：US14921855
申请日：2015-10-23
发明人： Douglas C. Burger , Aaron L. Smith
IPC分类号： G06F9/30 , G06F9/38 , G06F9/46 , G06F9/52 , G06F11/36 , G06F15/78 , G06F9/26 , G06F9/32 , G06F9/345 , G06F9/35 , G06F12/0806 , G06F12/0862 , G06F12/1009 , G06F13/42 , G06F15/80 , G06F9/355 , G06F12/0811 , G06F12/0875
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/3004 , G06F9/3005 , G06F9/30007 , G06F9/3009 , G06F9/30021 , G06F9/30036 , G06F9/30043 , G06F9/30047 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/30138 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/345 , G06F9/35 , G06F9/3802 , G06F9/383 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/3828 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0862 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F9/3013 , G06F9/321 , G06F9/355 , G06F9/3557 , G06F12/0811 , G06F12/0875 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/00
摘要： Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes selecting a next memory load or memory store instruction to execute based on dependencies encoded within the block, and on a store vector that stores data indicating which memory load and memory store instructions in the instruction block have executed. The store vector can be masked using a store mask. The store mask can be generated when decoding the instruction block, or copied from an instruction block header. Based on the encoded dependencies and the masked store vector, the next instruction can issue when its dependencies are available.
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公开(公告)号：US10061584B2
公开(公告)日：2018-08-28
申请号：US15060404
申请日：2016-03-03
发明人： Douglas C. Burger , Aaron L. Smith
IPC分类号： G06F9/312 , G06F9/44 , G06F9/30 , G06F15/80 , G06F9/32 , G06F9/38 , G06F9/26 , G06F11/36 , G06F12/0862 , G06F9/35 , G06F12/1009 , G06F13/42 , G06F15/78 , G06F9/46 , G06F9/52 , G06F12/0875 , G06F12/0811 , G06F12/0806
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30138 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/3828 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for nullifying memory store instructions identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions, based on a target field of the nullification instruction. The memory access instruction associated with the instruction identification is nullified. The memory access instruction is in a first instruction block of the plurality of instruction blocks. Based on the nullified memory access instruction, a subsequent memory access instruction from the first instruction block is executed.
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公开(公告)号：US20180067718A1
公开(公告)日：2018-03-08
申请号：US15807642
申请日：2017-11-09
发明人： Michael K. Gschwind
CPC分类号： G06F5/01 , G06F9/30134 , G06F9/35 , G06F9/355 , G11C19/00
摘要： Embodiments are directed to a processor for adjusting an index, wherein the index identifies a location of an element within an array. The processor includes a shift circuit configured to perform a single operation that adjusts a first parameter of the index to match a parameter of an array address. The single operation further adjusts a second parameter of the index to match a parameter of an array element.
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公开(公告)号：US09875082B2
公开(公告)日：2018-01-23
申请号：US14820770
申请日：2015-08-07
发明人： Michael K. Gschwind
CPC分类号： G06F5/01 , G06F9/30134 , G06F9/35 , G06F9/355 , G11C19/00
摘要： Embodiments are directed to a processor for adjusting an index, wherein the index identifies a location of an element within an array. The processor includes a shift circuit configured to perform a single operation that adjusts a first parameter of the index to match a parameter of an array address. The single operation further adjusts a second parameter of the index to match a parameter of an array element.
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公开(公告)号：US20170083340A1
公开(公告)日：2017-03-23
申请号：US15060483
申请日：2016-03-03
发明人： Douglas C. Burger , Aaron L. Smith
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for controlling instruction flow in block-based processor architectures. In one example of the disclosed technology, an instruction block address register stores an index address to a memory storing a plurality of instructions for an instruction block, the indexed address being inaccessible when the processor is in one or more unprivileged operational modes, one or more execution units configured to execute instructions for the instruction block, and a control unit configured to fetch and decode two or more of the plurality of instructions from the memory based on the indexed address.
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公开(公告)号：US20170083330A1
公开(公告)日：2017-03-23
申请号：US15060445
申请日：2016-03-03
发明人： Douglas C. Burger , Aaron L. Smith
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for nullifying memory store instructions and one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain an instruction identification for a memory access instruction of a plurality of memory access instructions and a register identification of at least one of a plurality of registers, based on a first and second target fields of the nullification instruction. The at least one register and the memory access instruction associated with the instruction identification are nullified. Based on the nullified memory access instruction, a subsequent memory access instruction is executed.
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公开(公告)号：US20170083324A1
公开(公告)日：2017-03-23
申请号：US14921855
申请日：2015-10-23
发明人： Douglas C. Burger , Aaron L. Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/3016 , G06F9/268 , G06F9/30007 , G06F9/30021 , G06F9/30036 , G06F9/3004 , G06F9/30043 , G06F9/30047 , G06F9/3005 , G06F9/30058 , G06F9/30072 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30101 , G06F9/30105 , G06F9/3013 , G06F9/30138 , G06F9/30145 , G06F9/30167 , G06F9/30189 , G06F9/32 , G06F9/321 , G06F9/345 , G06F9/35 , G06F9/355 , G06F9/3557 , G06F9/3802 , G06F9/3804 , G06F9/3822 , G06F9/3824 , G06F9/3828 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3848 , G06F9/3851 , G06F9/3853 , G06F9/3855 , G06F9/3859 , G06F9/3867 , G06F9/3891 , G06F9/466 , G06F9/528 , G06F11/36 , G06F11/3648 , G06F11/3656 , G06F12/0806 , G06F12/0811 , G06F12/0862 , G06F12/0875 , G06F12/1009 , G06F13/4221 , G06F15/7867 , G06F15/80 , G06F15/8007 , G06F2212/452 , G06F2212/602 , G06F2212/604 , G06F2212/62 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Apparatus and methods are disclosed for controlling execution of memory access instructions in a block-based processor architecture using a hardware structure that indicates a relative ordering of memory access instruction in an instruction block. In one example of the disclosed technology, a method of executing an instruction block having a plurality of memory load and/or memory store instructions includes selecting a next memory load or memory store instruction to execute based on dependencies encoded within the block, and on a store vector that stores data indicating which memory load and memory store instructions in the instruction block have executed. The store vector can be masked using a store mask. The store mask can be generated when decoding the instruction block, or copied from an instruction block header. Based on the encoded dependencies and the masked store vector, the next instruction can issue when its dependencies are available.
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