公开(公告)号：US09276598B1

公开(公告)日：2016-03-01

申请号：US14719931

申请日：2015-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Qunying Li ,  Joao Carlos Brito

IPC: H03M1/10 ,  H03M1/78 ,  H03M1/80 ,  H03M1/68

CPC classification number: H03M1/1057 ,  H03M1/687 ,  H03M1/785 ,  H03M1/808

Abstract: One or more high-order bit linear branches of a segmented DAC are implemented as R-2R networks geometrically down-scaled from the DAC binary portion by a selected factor. The resulting increase in closely-located mismatch is compensated for by implementing a trim circuit at a low-order end of each such linear branch. The trim circuit is designed with a number of trim steps to compensate for the selected linear branch down-scaling factor. Each trim step switches a resistance into the low-order end of the linear branch resulting in an even resistance increment or decrement at the lumped linear branch output. The trim circuit is calibrated to provide an amount of trim at the linear branch output such that the lumped resistance of the trimmed linear branch matches the lumped resistance of the binary portion within a selected tolerance (e.g., generally +/−0.5 LSB).

Abstract translation: 分段DAC的一个或多个高阶位线性分支被实现为从DAC二进制部分几何地缩小了选定因子的R-2R网络。 通过在每个这样的线性分支的低阶端实现微调电路来补偿由紧密定位的失配引起的增加。 微调电路设计有多个修整步骤，以补偿所选择的线性分支下标因子。 每个修整步骤将电阻切换到线性分支的低阶端，导致在集总线性分支输出处的均匀电阻增加或减小。 校准电路被校准以在线性分支输出处提供一定量的微调，使得修整的线性分支的集总电阻在所选公差（例如，一般为+/- 0.5LSB）内匹配二进制部分的集总电阻。

公开(公告)号：US11374571B2

公开(公告)日：2022-06-28

申请号：US17015645

申请日：2020-09-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joao Carlos Brito ,  Philip Anthony Coyle

IPC: H03K19/0175 ,  H01L23/528 ,  H03K19/21 ,  H01L23/495 ,  H01L23/00 ,  H01L23/522

Abstract: An integrated circuit provides a semiconductor die with I/O bond pads, a power bond pad, and a circuit ground pad. Each I/O bond pad is associated with an input circuit that has an input circuit output lead. Sets of digital logic functional circuitry on the die provide different digital logic functions. Each function includes logic input leads and logic output leads. Output circuits each have an output circuit in lead and an output circuit out lead. Strapping structures, such as vias, formed in the semiconductor die electrically couple input circuits to a selected set of digital logic functions and the selected set of digital logic functions to output circuit in leads. Upper level metal conductors couple output circuit out leads and selected I/O bond pads.

公开(公告)号：US10804900B2

公开(公告)日：2020-10-13

申请号：US16107388

申请日：2018-08-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joao Carlos Brito ,  Philip Anthony Coyle

IPC: H03K19/0175 ,  H01L23/528 ,  H03K19/21 ,  H01L23/495 ,  H01L23/00 ,  H01L23/522

Abstract: An integrated circuit provides a semiconductor die with I/O bond pads, a power bond pad, and a circuit ground pad. Each I/O bond pad is associated with an input circuit that has an input circuit output lead. Sets of digital logic functional circuitry on the die provide different digital logic functions. Each function includes logic input leads and logic output leads. Output circuits each have an output circuit in lead and an output circuit out lead. Strapping structures, such as vias, formed in the semiconductor die electrically couple input circuits to a selected set of digital logic functions and the selected set of digital logic functions to output circuit in leads. Upper level metal conductors couple output circuit out leads and selected I/O bond pads.

公开(公告)号：US20200067509A1

公开(公告)日：2020-02-27

申请号：US16107388

申请日：2018-08-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Joao Carlos Brito ,  Philip Anthony Coyle

IPC: H03K19/0175 ,  H01L23/528 ,  H01L23/522 ,  H01L23/495 ,  H01L23/00 ,  H03K19/21

Abstract: An integrated circuit provides a semiconductor die with I/O bond pads, a power bond pad, and a circuit ground pad. Each I/O bond pad is associated with an input circuit that has an input circuit output lead. Sets of digital logic functional circuitry on the die provide different digital logic functions. Each function includes logic input leads and logic output leads. Output circuits each have an output circuit in lead and an output circuit out lead. Strapping structures, such as vias, formed in the semiconductor die electrically couple input circuits to a selected set of digital logic functions and the selected set of digital logic functions to output circuit in leads. Upper level metal conductors couple output circuit out leads and selected I/O bond pads.