公开(公告)号：US20240310455A1

公开(公告)日：2024-09-19

申请号：US18227149

申请日：2023-07-27

Applicant: Texas Instruments Incorporated

Inventor： Karthik Anyam ,  Preetam Charan Anand Tadeparthy ,  Mayank Jain ,  Dattatreya Baragur Suryanarayana ,  Charan Hemanth Kumar

IPC: G01R31/40

CPC classification number: G01R31/40

Abstract: An example apparatus includes: a phase circuit configured to receive a pulse of a pulse width module (PWM) signal; provide, after receiving the pulse, an output voltage to a load; exhibit a fault; in response to the fault corresponding to a first category, transmit a first code voltage in a current sense (CS) signal; in response to the fault corresponding to a second category, transmit a reference voltage in the CS signal; receive, after transmission of the reference voltage, a tristate voltage in the PWM signal; and transmit, after receiving the tristate voltage, a second code voltage in the CS signal based on a type of the fault and the second category.

公开(公告)号：US20250062700A1

公开(公告)日：2025-02-20

申请号：US18451363

申请日：2023-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mohamed Ahmed ,  Matthew Schurmann ,  Preetam Tadeparthy ,  Rohit Narula ,  Vikram Gakhar ,  Vikas Lakhanpal ,  Karthik Anyam ,  Rengang Chen

IPC: H02M7/537

Abstract: A power controller comprises a control loop configured to control timing of pulsed signals that activate phases of a coupled inductor voltage regulator based on current demand of a load circuit and comprises a transient detection circuit configured to determine a projected current through a compensation inductor of the coupled inductor voltage regulator based on a state of the phases and operating parameters of the coupled inductor voltage regulator. The transient detection circuit is configured to detect a transient in the current demand of the load circuit based on a variability in phase-to-phase overlap of the pulsed signals. Responsive to detecting the transient, the transient detection circuit is configured to apply a correction to the control loop that alters the timing of the pulsed signals based on the projected current through the compensation inductor.

公开(公告)号：US12079054B2

公开(公告)日：2024-09-03

申请号：US17874696

申请日：2022-07-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Vishal Shaw ,  Preetam Tadeparthy ,  Mayank Jain ,  Karthik Anyam

IPC: G06F1/26 ,  H02M3/04 ,  H03M7/02

CPC classification number: G06F1/26 ,  H02M3/04 ,  H03M7/02

Abstract: One example includes a VID signal decoder circuit. The circuit includes a coarse resolution decoder that receives a VID signal. The VID signal can be encoded with a digital value of an output voltage. The coarse resolution decoder can decode the VID signal to generate a first digital signal. The circuit also includes a fine resolution decoder that receives the VID signal and to decode the VID signal to generate a second digital signal. The circuit further includes a multiplexer to provide the first digital signal as an output signal responsive to a first state of a selection signal and to provide the second digital signal as the output signal responsive to a second state of the selection signal. The first and second states of the selection signal can be based on a relative amplitude of the first and second digital signals.

公开(公告)号：US20240036624A1

公开(公告)日：2024-02-01

申请号：US17874696

申请日：2022-07-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： VISHAL SHAW ,  PREETAM TADEPARTHY ,  MAYANK JAIN ,  Karthik Anyam

IPC: G06F1/26 ,  H03M7/02 ,  H02M3/04

CPC classification number: G06F1/26 ,  H03M7/02 ,  H02M3/04

Abstract: One example includes a VID signal decoder circuit. The circuit includes a coarse resolution decoder that receives a VID signal. The VID signal can be encoded with a digital value of an output voltage. The coarse resolution decoder can decode the VID signal to generate a first digital signal. The circuit also includes a fine resolution decoder that receives the VID signal and to decode the VID signal to generate a second digital signal. The circuit further includes a multiplexer to provide the first digital signal as an output signal responsive to a first state of a selection signal and to provide the second digital signal as the output signal responsive to a second state of the selection signal. The first and second states of the selection signal can be based on a relative amplitude of the first and second digital signals.