CURRENT LIMIT FOR MULTIPHASE POWER CONVERTERS

    公开(公告)号:US20250062678A1

    公开(公告)日:2025-02-20

    申请号:US18425138

    申请日:2024-01-29

    Abstract: Described embodiments include a control circuit with a first comparator having a first comparator input receiving a first threshold voltage, and a second comparator input coupled to an output voltage terminal. A second comparator has a third comparator input receiving a second threshold voltage, and a fourth comparator input coupled to a current output terminal. A first logic circuit provides a true signal at its output responsive to a particular number of its inputs receiving a true input. A second logic circuit has inputs coupled to the first comparator output, and to the first logic output. A variable resistance circuit has an output coupled to a mode detection output. An amplifier has inputs coupled to the variable resistance circuit output, and a third reference voltage source. A duty cycle generation circuit provides a respective pulse width modulation (PWM) signal at each of its respective duty cycle outputs.

    Pinstrap detection circuit
    4.
    发明授权

    公开(公告)号:US11211940B2

    公开(公告)日:2021-12-28

    申请号:US16732213

    申请日:2019-12-31

    Abstract: In at least some examples, an integrated circuit includes an input pin and an analog-to-digital converter (ADC) comprising an input terminal coupled to the input pin and an output terminal. The integrated circuit further includes a logic circuit comprising an input terminal coupled to the output terminal of the ADC, a first output terminal, and a second output terminal. The integrated circuit further includes a resistance circuit. In an example, the resistance circuit includes a resistor coupled between the input pin and a first node, a first switch coupled between the first node and a reference voltage pin, and a second switch coupled between the first node and a ground pin.

    POWER CONVERTER CONTROL
    10.
    发明公开

    公开(公告)号:US20240039402A1

    公开(公告)日:2024-02-01

    申请号:US18376230

    申请日:2023-10-03

    CPC classification number: H02M3/155 H03K5/24 H02M1/08

    Abstract: In some examples, a circuit includes a state machine. The state machine is configured to operate in a first state in which the state machine gates a pulse width modulation (PWM) signal provided for control of a power converter according to a first signal provided by a voltage control loop. The state machine is configured to operate in a second state in which the state machine gates the PWM signal according to a second signal provided by a current limit comparator. The state machine is configured to transition from the first state to the second state responsive to the second signal being asserted after the first signal is asserted in a switching cycle of the power converter. The state machine is configured to transition from the current state to the first state responsive to the first signal being asserted after the second signal in a switching cycle of the power converter.

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