公开(公告)号：US11750155B2

公开(公告)日：2023-09-05

申请号：US17470985

申请日：2021-09-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aniruddha Roy ,  Kunal Suresh Karanjkar

IPC: H03F3/20 ,  H03F3/45

CPC classification number: H03F3/20

Abstract: Aspects of the description provide for a circuit. In some examples, the circuit includes a input pair of transistors, a bias transistor having a bias transistor gate, a bias transistor drain, and a bias transistor source, the bias transistor drain coupled to the input pair of transistors and the bias transistor source coupled to ground, and a resistor coupled between the bias transistor gate and the input pair of transistors.

公开(公告)号：US11955964B2

公开(公告)日：2024-04-09

申请号：US17169638

申请日：2021-02-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nitin Agarwal ,  Kunal Suresh Karanjkar ,  Venkata Ramanan R

IPC: H03K17/693 ,  H03F3/72 ,  H03K17/00 ,  H03K17/10

CPC classification number: H03K17/693 ,  H03F3/72 ,  H03K17/005 ,  H03K17/102

Abstract: A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.

公开(公告)号：US10917090B1

公开(公告)日：2021-02-09

申请号：US16700444

申请日：2019-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nitin Agarwal ,  Kunal Suresh Karanjkar ,  Venkata Ramanan R

IPC: H03K17/693 ,  H03K17/10 ,  H03K17/00 ,  H03F3/72

Abstract: A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.