公开(公告)号：US11742812B2

公开(公告)日：2023-08-29

申请号：US17242971

申请日：2021-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aniruddha Roy ,  Saurabh Pandey

IPC: H03F3/45 ,  H03F3/68

CPC classification number: H03F3/45246 ,  H03F3/68 ,  H03F2203/45288 ,  H03F2203/45344 ,  H03F2203/45356 ,  H03F2203/45374

Abstract: A circuit includes a first transconductance stage having an output. The circuit further includes an output transconductance stage, and a first source-degenerated transistor having a first control input and first and second current terminals. The first control input is coupled to the output of the first transconductance stage. The circuit also includes a second transistor having a second control input and third and fourth current terminals. The third current terminal is coupled to the second current terminal and to the output transconductance stage.

公开(公告)号：US20230246595A1

公开(公告)日：2023-08-03

申请号：US18298626

申请日：2023-04-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nitin Agarwal ,  Aniruddha Roy

IPC: H03F1/02 ,  H03F1/32

CPC classification number: H03F1/0233 ,  H03F1/3205 ,  H03F2200/504

Abstract: A circuit is provided. In some examples, the circuit includes a first transistor having a gate and a drain coupled together and a current source coupled to the drain of the first transistor. A second transistor has a drain coupled to a source of the first transistor. A third transistor has a gate coupled to the gate of the first transistor. A fourth transistor has a drain coupled to a source of the third transistor and a gate of the fourth transistor is coupled to a gate of the second transistor. In some examples, the third transistor is configured to limit a first current between the third transistor and the fourth transistor based on an output voltage.

公开(公告)号：US20220014151A1

公开(公告)日：2022-01-13

申请号：US17136427

申请日：2020-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nitin Agarwal ,  Aniruddha Roy

IPC: H03F1/02 ,  H03F1/32

Abstract: A circuit is provided. In some examples, the circuit includes a first transistor having a gate and a drain coupled together and a current source coupled to the drain of the first transistor. A second transistor has a drain coupled to a source of the first transistor. A third transistor has a gate coupled to the gate of the first transistor. A fourth transistor has a drain coupled to a source of the third transistor and a gate of the fourth transistor is coupled to a gate of the second transistor. In some examples, the third transistor is configured to limit a first current between the third transistor and the fourth transistor based on an output voltage.

公开(公告)号：US20170149398A1

公开(公告)日：2017-05-25

申请号：US15144531

申请日：2016-05-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nitin Agarwal ,  Aniruddha Roy

IPC: H03G1/00 ,  H03K5/08 ,  H02M3/07 ,  H03H19/00

CPC classification number: H03G1/0094 ,  H02M3/07 ,  H03G1/0029 ,  H03G3/001 ,  H03G5/28 ,  H03K5/08

Abstract: A compensation circuit includes an amplifier coupled between a first voltage terminal and a common terminal. The amplifier has a first output terminal. A current source transistor has a current path coupled between a second voltage terminal and a second output terminal. A threshold voltage sense transistor has a current path coupled between the first and second output terminals. A gate and drain of the threshold voltage sense transistor are connected. An output transistor having a current path coupled between the first output terminal and a third output terminal has a gate coupled to the second output terminal.

公开(公告)号：US11949417B2

公开(公告)日：2024-04-02

申请号：US17838029

申请日：2022-06-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Aniruddha Roy ,  Nitin Agarwal ,  Rajavelu Thinakaran

IPC: H03K3/0231 ,  G05F1/567 ,  G05F3/24 ,  G05F3/26 ,  H03K3/011 ,  H03K4/502

CPC classification number: H03K3/0231 ,  G05F1/567 ,  G05F3/245 ,  G05F3/262 ,  H03K3/011 ,  H03K4/502

Abstract: Trimming components within an oscillator comprising: a trim-capable current source, wherein the trim-capable current source comprises a trimmable resistor and a trimmable current component, a comparator comprising a first input terminal that couples to the trim-capable current source and the second input terminal that couples to a reference voltage source, a switch coupled to the first input terminal and the trim-capable current source, and a trim-capable capacitor coupled to the switch, wherein the switch is coupled between the trim-capable capacitor and the trim-capable current source.

公开(公告)号：US11626841B2

公开(公告)日：2023-04-11

申请号：US17136427

申请日：2020-12-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nitin Agarwal ,  Aniruddha Roy

IPC: H03F1/02 ,  H03F1/32

Abstract: A circuit is provided. In some examples, the circuit includes a first transistor having a gate and a drain coupled together and a current source coupled to the drain of the first transistor. A second transistor has a drain coupled to a source of the first transistor. A third transistor has a gate coupled to the gate of the first transistor. A fourth transistor has a drain coupled to a source of the third transistor and a gate of the fourth transistor is coupled to a gate of the second transistor. In some examples, the third transistor is configured to limit a first current between the third transistor and the fourth transistor based on an output voltage.

公开(公告)号：US11437955B1

公开(公告)日：2022-09-06

申请号：US17510032

申请日：2021-10-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nitin Agarwal ,  Aniruddha Roy ,  Preetham Narayana Reddy

IPC: H03B5/06 ,  H03B5/12 ,  H03L5/00 ,  H03B5/36

Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin of the chip. The oscillator circuit also includes a first switch coupled to the pin, a second switch coupled to the pin and to a charging resistor, and a third switch coupled to the amplifier and an internal resistor, where the internal resistor is internal to the chip. The oscillator circuit includes a bias current source coupled to the current mirror. The system includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system also includes an external capacitor coupled to the pin and coupled in parallel to the external resistor, where the external capacitor is external to the chip.

公开(公告)号：US11070180B2

公开(公告)日：2021-07-20

申请号：US16395334

申请日：2019-04-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nitin Agarwal ,  Aniruddha Roy

IPC: H03F3/45 ,  H03F3/30 ,  H03F1/22

Abstract: A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.

公开(公告)号：US11984849B2

公开(公告)日：2024-05-14

申请号：US17903128

申请日：2022-09-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nitin Agarwal ,  Aniruddha Roy ,  Preetham Narayana Reddy

IPC: H03B5/06 ,  H03B5/12 ,  H03B5/36 ,  H03L5/00

CPC classification number: H03B5/06 ,  H03B5/1212 ,  H03B5/36 ,  H03L5/00

Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror and an amplifier, where the amplifier is coupled to a pin of the chip. The oscillator circuit also includes a first switch coupled to the pin, a second switch coupled to the pin and to a charging resistor, and a third switch coupled to the amplifier and an internal resistor, where the internal resistor is internal to the chip. The oscillator circuit includes a bias current source coupled to the current mirror. The system includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system also includes an external capacitor coupled to the pin and coupled in parallel to the external resistor, where the external capacitor is external to the chip.

公开(公告)号：US11848645B2

公开(公告)日：2023-12-19

申请号：US17509706

申请日：2021-10-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nitin Agarwal ,  Aniruddha Roy ,  Preetham Narayana Reddy

IPC: H03K3/0231 ,  H03B5/20

CPC classification number: H03B5/20 ,  H03K3/0231 ,  H03B2200/0014 ,  H03B2200/0034 ,  H03B2200/0038

Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror, an amplifier, and an on-chip resistor, where the on-chip resistor is coupled to a pin on the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first resistor, and a second capacitor coupled to a second resistor. The system also includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system includes an external capacitor coupled to the pin, where the external capacitor is external to the chip.