公开(公告)号：US20200011917A1

公开(公告)日：2020-01-09

申请号：US16409119

申请日：2019-05-10

Applicant: Texas Instruments Incorporated

Inventor： Bhaskar RAMACHANDRAN ,  Kushal D. MURTHY

IPC: G01R31/02 ,  H03K17/0814

Abstract: In described examples, a circuit includes a first driver. The first driver is coupled to a first node, and the first node is coupled to an output pin. A second driver is coupled to a second node, and the second node is coupled to a first voltage terminal. A comparator is coupled to the first node and the second node. A sustaining driver is coupled to the comparator and provides a threshold current to each of the first node and the second node when a short is detected at the output pin.

公开(公告)号：US20170337985A1

公开(公告)日：2017-11-23

申请号：US15597820

申请日：2017-05-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Anindita BORAH ,  Muthusubramanian VENKATESWARAN ,  Kushal D. MURTHY ,  Vikram GAKHAR ,  Preetam TADEPARTHY

IPC: G11C29/38 ,  G11C14/00 ,  G11C17/08 ,  G11C29/36

CPC classification number: G11C29/38 ,  G11C17/08 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C29/12 ,  G11C29/36

Abstract: A one-time programmable (OTP) circuit. The OTP circuit includes a non-volatile OTP memory disposed on a first circuit die. The OTP memory includes a floating gate terminal. The OTP circuit also includes a cross-coupled latch disposed on the first circuit die and coupled to the OTP memory and volatile memory input circuitry disposed on the first circuit die and coupled to the cross-coupled latch. The volatile memory input circuitry is configured to receive a test value and write the test value into the cross-coupled latch. The OTP circuit is configured to receive a programming command and store the test value in the OTP memory in response to receipt of the programming command.

公开(公告)号：US20200011906A1

公开(公告)日：2020-01-09

申请号：US16230564

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bhaskar RAMACHANDRAN ,  Kushal D. MURTHY ,  Aalok Dyuti SAHA

IPC: G01R19/165 ,  G01R19/155

Abstract: A device includes a first transistor coupled to an input voltage source and to an output voltage node and an amplifier comprising a first input, a second input, and an output. The device also includes a second transistor coupled to the input voltage source and the first input of the amplifier and a third transistor coupled to the second transistor and a ground node. The third transistor includes a control terminal coupled to the output of the amplifier. The device also includes a first voltage-controlled voltage source coupled to a control terminal of the first transistor and a control terminal of the second transistor and a second voltage-controlled voltage source coupled to the first transistor and the second input of the amplifier.