RECEIVER WITH PRE-CURSOR INTERSYMBOL INTERFERENCE MITIGATION

    公开(公告)号:US20240137198A1

    公开(公告)日:2024-04-25

    申请号:US18309587

    申请日:2023-04-27

    CPC classification number: H04L7/0016 H04L25/03012

    Abstract: A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.

    RECEIVER WITH PRE-CURSOR INTERSYMBOL INTERFERENCE MITIGATION

    公开(公告)号:US20240235804A9

    公开(公告)日:2024-07-11

    申请号:US18309587

    申请日:2023-04-28

    CPC classification number: H04L7/0016 H04L25/03012

    Abstract: A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.

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