公开(公告)号：US20240137198A1

公开(公告)日：2024-04-25

申请号：US18309587

申请日：2023-04-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek MANIAN ,  Ashkan ROSHAN ZAMIR ,  Yonghui TANG ,  Robin GUPTA ,  Michael G. VRAZEL

IPC: H04L7/00 ,  H04L25/03

CPC classification number: H04L7/0016 ,  H04L25/03012

Abstract: A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.

公开(公告)号：US20240235804A9

公开(公告)日：2024-07-11

申请号：US18309587

申请日：2023-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek MANIAN ,  Ashkan ROSHAN ZAMIR ,  Yonghui TANG ,  Robin GUPTA ,  Michael G. VRAZEL

IPC: H04L7/00 ,  H04L25/03

CPC classification number: H04L7/0016 ,  H04L25/03012

Abstract: A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.

公开(公告)号：US20210409014A1

公开(公告)日：2021-12-30

申请号：US17084901

申请日：2020-10-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek MANIAN ,  Surya Theja GOLAKONDA ,  Robin GUPTA

IPC: H03K5/14 ,  H03L7/081

Abstract: A clockless delay adaptation loop configured to adapt to random data includes a first and a second delay line, an autocorrelator, and a controller. The autocorrelator receives an input signal for the delay adaptation loop and the output from the first delay line, and includes a first logic circuit configured to output a first autocorrelation and a second logic circuit configured to output a second autocorrelation. The controller is configured generate a control signal for one of the first and second delay lines based on the first and second autocorrelations. In some examples, the first logic circuit is an XNOR gate, and the second logic circuit is an OR gate. In some examples, the OR gate can have a gain that is two times a gain of the XNOR gate. In some examples, an amplifier having two times the gain of the XNOR gate is coupled to the OR gate.