公开(公告)号：US20230039848A1

公开(公告)日：2023-02-09

申请号：US17968978

申请日：2022-10-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yonghui TANG ,  Yanli FAN

IPC: G06F13/40 ,  G06F13/42 ,  H03K5/1534 ,  H03K5/24

Abstract: In an embodiment, a current source is coupled to a first current terminal of a switch, the second current terminal of which is coupled to a first data line in a communication system. An edge detector has a first input, a second input, and an output, in which the first input is coupled to a second data line in the communication system, the second input is coupled to the first data line, and the output is coupled to a control terminal of the switch. The first and second data lines may be positive and negative data lines, respectively, of the communication system.

公开(公告)号：US20200059224A1

公开(公告)日：2020-02-20

申请号：US16367381

申请日：2019-03-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yanfei JIANG ,  Huanzhang HUANG ,  Yonghui TANG ,  Shita GUO

IPC: H03K5/00 ,  H03K5/1252 ,  G05F1/46 ,  H03K19/20 ,  H03K19/0175

Abstract: Aspects of the disclosure provide for a method. In some examples, the method includes detecting a transition in an input signal (IN), generating a bias current based on the detected transition in IN, and modifying a charge status of a capacitor based on the charge current. The method further includes generating an output signal (OUT) based on the charge status of the capacitor, disabling the bias current generation based on values of IN and OUT, and strongly pulling the capacitor up or down based on the disabling the bias current generation.

公开(公告)号：US20240320178A1

公开(公告)日：2024-09-26

申请号：US18672723

申请日：2024-05-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yonghui TANG ,  Yanli FAN

IPC: G06F13/40 ,  G06F13/42 ,  H03K5/1534 ,  H03K5/24

CPC classification number: G06F13/4022 ,  G06F13/4063 ,  G06F13/4282 ,  G06F13/4295 ,  G06F2213/0042 ,  H03K5/1534 ,  H03K5/24

Abstract: In an embodiment, a current source is coupled to a first current terminal of a switch, the second current terminal of which is coupled to a first data line in a communication system. An edge detector has a first input, a second input, and an output, in which the first input is coupled to a second data line in the communication system, the second input is coupled to the first data line, and the output is coupled to a control terminal of the switch. The first and second data lines may be positive and negative data lines, respectively, of the communication system.

公开(公告)号：US20210311903A1

公开(公告)日：2021-10-07

申请号：US17347920

申请日：2021-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing MAUNG ,  Suzanne Mary VINING ,  Yonghui TANG ,  Douglas Edward WENTE ,  Huanzhang HUANG

IPC: G06F13/42

Abstract: A serial bus signal conditioner circuit includes receiver circuitry, a mode identification circuit, and an edge-rate booster circuit. The receiver circuitry is configured to receive signals transmitted on a serial bus. The mode identification circuit is coupled to the receiver circuitry, and is configured to identify initiation of or return to high-speed signaling on the serial bus based on sequences of the signals transmitted on the serial bus. The edge-rate booster circuit is coupled to the mode identification circuit, and is configured to identify edges of a differential signal transmitted on the serial bus, and to supply a differential current to the serial bus based on identification of an edge of the differential signal.

公开(公告)号：US20200057742A1

公开(公告)日：2020-02-20

申请号：US16414496

申请日：2019-05-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing MAUNG ,  Yonghui TANG ,  Huanzhang HUANG ,  Douglas Edward WENTE

IPC: G06F13/40 ,  G06F13/42

Abstract: Aspects of the present disclosure provide for a system. In at least some examples, the system includes an embedded Universal Serial Bus 2 (eUSB2) device having a first receiver and a first transmitter, a processor, a second transmitter coupled to the processor, a second receiver coupled to the processor, a drive low circuit coupled to the processor second transmitter, and differential signal lines having a length greater than ten inches. The differential signal lines are coupled at a first end to the first receiver and the first transmitter and at a second end to the second transmitter and the second receiver. The processor is configured to control the drive low circuit to drive the differential signal lines low with a logic ‘0’ to cause the first receiver to receive the logic ‘0’ and a value of a signal present on the differential signal lines to reach about 0 volts.

公开(公告)号：US20240235804A9

公开(公告)日：2024-07-11

申请号：US18309587

申请日：2023-04-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek MANIAN ,  Ashkan ROSHAN ZAMIR ,  Yonghui TANG ,  Robin GUPTA ,  Michael G. VRAZEL

IPC: H04L7/00 ,  H04L25/03

CPC classification number: H04L7/0016 ,  H04L25/03012

Abstract: A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.

公开(公告)号：US20210311898A1

公开(公告)日：2021-10-07

申请号：US17347882

申请日：2021-06-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Win Naing MAUNG ,  Yonghui TANG ,  Huanzhang HUANG ,  Douglas Edward WENTE

IPC: G06F13/40 ,  G06F13/42

Abstract: Aspects of the present disclosure provide for a system. In at least some examples, the system includes an embedded Universal Serial Bus 2 (eUSB2) device having a first receiver and a first transmitter, a processor, a second transmitter coupled to the processor, a second receiver coupled to the processor, a drive low circuit coupled to the processor second transmitter, and differential signal lines having a length greater than ten inches. The differential signal lines are coupled at a first end to the first receiver and the first transmitter and at a second end to the second transmitter and the second receiver. The processor is configured to control the drive low circuit to drive the differential signal lines low with a logic ‘0’ to cause the first receiver to receive the logic ‘0’ and a value of a signal present on the differential signal lines to reach about 0 volts.

公开(公告)号：US20190213158A1

公开(公告)日：2019-07-11

申请号：US15967883

申请日：2018-05-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yonghui TANG ,  Yanli FAN

IPC: G06F13/40 ,  G06F13/42

Abstract: In one embodiment, a current source is coupled to a channel input of a switch, and an output of the switch is coupled to a positive or negative data line in a USB 2.0 communication system. In addition, a first input of the voltage threshold comparator is coupled to the negative data line, a second input of the voltage threshold comparator is coupled to a positive data line, and an output of the voltage threshold comparator is coupled to a control input of the switch.

公开(公告)号：US20240137198A1

公开(公告)日：2024-04-25

申请号：US18309587

申请日：2023-04-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abishek MANIAN ,  Ashkan ROSHAN ZAMIR ,  Yonghui TANG ,  Robin GUPTA ,  Michael G. VRAZEL

IPC: H04L7/00 ,  H04L25/03

CPC classification number: H04L7/0016 ,  H04L25/03012

Abstract: A receiver includes: equalizer circuitry; clock and data recovery (CDR) circuitry; sampler circuitry; adaptation circuitry; and clock adjustment circuitry. The receiver is configured to: receive data via a channel; perform equalization operations on received data, the equalization operations resulting in equalization results; perform sampling operations responsive to the equalization results, the sampling operations resulting in data samples and error samples; perform adaptation operations responsive to the data samples and the error samples, the adaptation operations resulting in a clock adjustment control signal; and adjust a sampling clock signal relative to a CDR clock signal responsive to the clock adjustment control signal.

公开(公告)号：US20200327082A1

公开(公告)日：2020-10-15

申请号：US16915751

申请日：2020-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yonghui TANG ,  Yanli FAN

IPC: G06F13/40 ,  G06F13/42

Abstract: In one embodiment, a current source is coupled to a channel input of a switch, and an output of the switch is coupled to a positive or negative data line in a USB 2.0 communication system. In addition, a first input of the voltage threshold comparator is coupled to the negative data line, a second input of the voltage threshold comparator is coupled to a positive data line, and an output of the voltage threshold comparator is coupled to a control input of the switch.