公开(公告)号：US11474944B2

公开(公告)日：2022-10-18

申请号：US17151857

申请日：2021-01-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Ramakrishnan Venkatasubramanian ,  Hung Ong

IPC: G06F12/0862 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0875 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0888 ,  G06F12/1027

Abstract: This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional program instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetches the lower half level two cache line employing fewer resources than an ordinary prefetch.

公开(公告)号：US20210141732A1

公开(公告)日：2021-05-13

申请号：US17151857

申请日：2021-01-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Ramakrishnan Venkatasubramanian ,  Hung Ong

IPC: G06F12/0862 ,  G06F12/0875 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/0815

Abstract: This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional program instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetches the lower half level two cache line employing fewer resources than an ordinary prefetch.

公开(公告)号：US20200167288A1

公开(公告)日：2020-05-28

申请号：US16775479

申请日：2020-01-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Ramakrishnan Venkatasubramanian

IPC: G06F12/0862 ,  G06F12/1027 ,  G06F9/38 ,  G06F12/02 ,  G06F12/0871

Abstract: Disclosed embodiments provide a technique in which a memory controller determines whether a fetch address is a miss in an L1 cache and, when a miss occurs, allocates a way of the L1 cache, determines whether the allocated way matches a scoreboard entry of pending service requests, and, when such a match is found, determine whether a request address of the matching scoreboard entry matches the fetch address. When the matching scoreboard entry also has a request address matching the fetch address, the scoreboard entry is modified to a demand request.

公开(公告)号：US12197334B2

公开(公告)日：2025-01-14

申请号：US17940070

申请日：2022-09-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Ramakrishnan Venkatasubramanian ,  Hung Ong

IPC: G06F12/0862 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0888 ,  G06F12/1027

Abstract: This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional program instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetches the lower half level two cache line employing fewer resources than an ordinary prefetch.

公开(公告)号：US20240419602A1

公开(公告)日：2024-12-19

申请号：US18820740

申请日：2024-08-30

Applicant: Texas Instruments Incorporated

Inventor： Oluleye Olorode ,  Ramakrishnan Venkatasubramanian

IPC: G06F12/0862 ,  G06F9/38 ,  G06F12/02 ,  G06F12/0871 ,  G06F12/1027

Abstract: Disclosed embodiments provide a technique in which a memory controller determines whether a fetch address is a miss in an L1 cache and, when a miss occurs, allocates a way of the L1 cache, determines whether the allocated way matches a scoreboard entry of pending service requests, and, when such a match is found, determine whether a request address of the matching scoreboard entry matches the fetch address. When the matching scoreboard entry also has a request address matching the fetch address, the scoreboard entry is modified to a demand request.

公开(公告)号：US20190227619A1

公开(公告)日：2019-07-25

申请号：US16253363

申请日：2019-01-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Mehrdad Nourani

IPC: G06F1/3234 ,  G06F12/0846 ,  G06F12/0895 ,  G06F12/0811

CPC classification number: G06F1/3275 ,  G06F12/0811 ,  G06F12/0848 ,  G06F12/0895 ,  G06F2212/1028 ,  G06F2212/282 ,  G06F2212/283 ,  Y02D10/13

Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

公开(公告)号：US10191534B2

公开(公告)日：2019-01-29

申请号：US15804785

申请日：2017-11-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Mehrdad Nourani

IPC: G06F12/0846 ,  G06F12/0895 ,  G06F1/32 ,  G06F12/0811

Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

公开(公告)号：US20250013284A1

公开(公告)日：2025-01-09

申请号：US18894180

申请日：2024-09-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Mehrdad Nourani

IPC: G06F1/3234 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0895

Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

公开(公告)号：US20220091659A1

公开(公告)日：2022-03-24

申请号：US17541776

申请日：2021-12-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Mehrdad Nourani

IPC: G06F1/3234 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/0846

Abstract: Disclosed embodiments relate to a dNap architecture that accurately transitions cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

公开(公告)号：US10210090B1

公开(公告)日：2019-02-19

申请号：US15730893

申请日：2017-10-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Oluleye Olorode ,  Ramakrishnan Venkatasubramanian

IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/02 ,  G06F9/38 ,  G06F12/1027

Abstract: This invention involves a particular cache hazard. It is possible that an instruction request that is a miss in the cache occurs while the cache system is servicing a pending prefetch for the same instructions. In the prior art, this hazard is detected by comparing request addresses for all entries in a scoreboard. The program memory controller stores the allocated way in the scoreboard. The program memory controller compares the allocated way of the demand request to the allocated way of all the scoreboard entries. The cache hazard only occurs when the allocated ways match. Following way compare, the demand request address is compared to the request addresses of only those scoreboard entries having matching ways. Other address comparators are not powered during this time. This serves to reduce the electrical power required in detecting this cache hazard.