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公开(公告)号：US20220245069A1
公开(公告)日：2022-08-04
申请号：US17727921
申请日：2022-04-25
发明人： Bipin Prasad Heremagalur Ramaprasad , David Matthew Thompson , Abhijeet Ashok Chachad , Hung Ong
IPC分类号： G06F12/1045 , G06F15/78
摘要： A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.
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公开(公告)号：US20240256464A1
公开(公告)日：2024-08-01
申请号：US18630098
申请日：2024-04-09
发明人： Bipin Prasad Heremagalur Ramaprasad , David Matthew Thompson , Abhijeet Ashok Chachad , Hung Ong
IPC分类号： G06F12/1045 , G06F15/78
CPC分类号： G06F12/1045 , G06F15/7807 , G06F2212/301 , G06F2212/50
摘要： A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.
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公开(公告)号：US20160019151A1
公开(公告)日：2016-01-21
申请号：US14335351
申请日：2014-07-18
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F9/30036 , G06F9/30072 , G06F9/30094 , G06F9/30112 , G06F9/3013 , G06F9/38 , G06F9/3836 , G06F9/3838 , G06F9/3853 , G06F9/3855 , G06F9/3873 , G06F12/0804 , G06F12/0811 , G06F12/0875 , G06F12/0897 , G06F2212/452 , G06F2212/60 , G06F2212/621
摘要： A method is shown that eliminates the need for a dedicated reorder buffer register bank or memory space in a multi level cache system. As data requests from the L2 cache may be returned out of order, the L1 cache uses it's cache memory to buffer the out of order data and provides the data to the requesting processor in the correct order from the buffer.
摘要翻译： 示出了一种方法，其消除了对多级缓存系统中的专用重排缓冲寄存器组或存储器空间的需要。 由于来自L2高速缓存的数据请求可能无法返回，所以L1高速缓存使用其高速缓冲存储器来缓冲乱序数据，并以缓冲器的正确顺序向请求处理器提供数据。
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公开(公告)号：US20230251975A1
公开(公告)日：2023-08-10
申请号：US18194708
申请日：2023-04-03
发明人： Bipin Prasad Heremagalur Ramaprasad , David Matthew Thompson , Abhijeet Ashok Chachad , Hung Ong
IPC分类号： G06F12/1045 , G06F15/78
CPC分类号： G06F12/1045 , G06F15/7807 , G06F2212/50 , G06F2212/301
摘要： A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.
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公开(公告)号：US11474944B2
公开(公告)日：2022-10-18
申请号：US17151857
申请日：2021-01-19
IPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0815 , G06F12/0875 , G06F9/30 , G06F9/38 , G06F12/0888 , G06F12/1027
摘要： This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional program instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetches the lower half level two cache line employing fewer resources than an ordinary prefetch.
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公开(公告)号：US20210141732A1
公开(公告)日：2021-05-13
申请号：US17151857
申请日：2021-01-19
IPC分类号： G06F12/0862 , G06F12/0875 , G06F9/30 , G06F9/38 , G06F12/0811 , G06F12/0815
摘要： This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional program instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetches the lower half level two cache line employing fewer resources than an ordinary prefetch.
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公开(公告)号：US20230004498A1
公开(公告)日：2023-01-05
申请号：US17940070
申请日：2022-09-08
IPC分类号： G06F12/0862 , G06F12/0875 , G06F9/30 , G06F9/38 , G06F12/0811 , G06F12/0815
摘要： This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional program instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetches the lower half level two cache line employing fewer resources than an ordinary prefetch.
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公开(公告)号：US10929296B2
公开(公告)日：2021-02-23
申请号：US15730874
申请日：2017-10-12
IPC分类号： G06F12/0862 , G06F12/0875 , G06F9/30 , G06F9/38 , G06F12/0811 , G06F12/0815 , G06F12/0888 , G06F12/1027
摘要： This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional program instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetches the lower half level two cache line employing fewer resources than an ordinary prefetch.
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公开(公告)号：US20200089622A1
公开(公告)日：2020-03-19
申请号：US16694751
申请日：2019-11-25
发明人： Bipin Prasad Heremagalur Ramaprasad , David Matthew Thompson , Abhijeet Ashok Chachad , Hung Ong
IPC分类号： G06F12/1045 , G06F15/78
摘要： A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.
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公开(公告)号：US20190114263A1
公开(公告)日：2019-04-18
申请号：US15730874
申请日：2017-10-12
IPC分类号： G06F12/0862 , G06F12/0811 , G06F12/0815 , G06F12/0888 , G06F12/1027 , G06F9/30 , G06F9/38
摘要： This invention involves a cache system in a digital data processing apparatus including: a central processing unit core; a level one instruction cache; and a level two cache. The cache lines in the second level cache are twice the size of the cache lines in the first level instruction cache. The central processing unit core requests additional program instructions when needed via a request address. Upon a miss in the level one instruction cache that causes a hit in the upper half of a level two cache line, the level two cache supplies the upper half level cache line to the level one instruction cache. On a following level two cache memory cycle, the level two cache supplies the lower half of the cache line to the level one instruction cache. This cache technique thus prefetchs the lower half level two cache line employing fewer resources than an ordinary prefetch.
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