HARDWARE ACCELERATION FOR PIPELINED VECTOR OPERATIONS

    公开(公告)号:US20240143282A1

    公开(公告)日:2024-05-02

    申请号:US17977813

    申请日:2022-10-31

    CPC classification number: G06F7/57 G06F17/16

    Abstract: In described examples, an integrated circuit includes an output terminal coupled to an input of a power amplifier, a feedback terminal coupled to an output of the power amplifier, a data terminal that receives a data stream, and a digital pre-distortion (DPD) circuit. The DPD circuit includes a capture circuit, a DPD estimator responsive to the data stream and the feedback terminal, and a DPD corrector responsive to the DPD estimator. The DPD estimator includes an instruction memory configured to store instructions and a vector arithmetic processing unit (APU) coupled to the instruction memory. The vector APU includes vector memories, vector arithmetic blocks, and an instruction decode block. The vector arithmetic blocks include vector addition blocks and vector multiplication blocks. The instruction decode block is configured to cause the vector APU to perform complex domain vector arithmetic on vectors stored in the vector memories in response to the instructions.

    METHODS AND APPARATUS TO ESTIMATE PRE-DISTORTION COEFFICIENTS

    公开(公告)号:US20240184846A1

    公开(公告)日:2024-06-06

    申请号:US18129589

    申请日:2023-03-31

    CPC classification number: G06F17/16

    Abstract: An example apparatus includes: programmable circuitry to receive an input signal, a digital pre-distorter (DPD) output signal, and a power amplifier (PA) feedback signal; populate a partial matrix with a threshold number of rows of equation terms; compute a respective observation terms for each row in the threshold number of rows; reduce the partial matrix into a Hermitian matrix and reduce the observation terms into a vector; accumulate the Hermitian matrix and the vector onto the memory; regularize, after a determination that a threshold number of Hermitian matrices have been accumulated, the memory to form an output matrix; and pre-distort the input signal using the output matrix.

    Enhancing TX-TX isolation through digital pre-compensation

    公开(公告)号:US11757479B2

    公开(公告)日:2023-09-12

    申请号:US17489381

    申请日:2021-09-29

    CPC classification number: H04B1/0475 H03G3/3036 H03G2201/106

    Abstract: A TX-TX pre-compensation system that estimates unwanted coupling in a victim transmit chain caused by an aggressor transmit chain and injects a pre-compensation signal to cancel out the estimated coupling. In some embodiments, a signal measurement module estimates the amplitude, phase, and envelope delay of the coupling and an isolation pre-compensation module generates the pre-compensation signal based on the estimated amplitude, the estimated phase, the estimated envelope delay, and the difference between the carrier frequencies of the transmit chains. Since the phase of the coupling may be affected by the carrier frequency of the transmit chains, in some embodiments the phase of the pre-compensation signal is adjusted in response to a change in carrier frequency. Since the amplitude of the coupling may be affected by attenuator gain settings, in some embodiments the amplitude of the pre-compensation signal may be adjusted in response to a change in attenuator gain setting.

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