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    PEAK-TO-AVERAGE POWER REDUCTION USING GUARD TONE FILTERING
    4.
    发明申请
    PEAK-TO-AVERAGE POWER REDUCTION USING GUARD TONE FILTERING 审中-公开

    公开(公告)号：US20180227157A1

    公开(公告)日：2018-08-09

    申请号：US15942614

    申请日：2018-04-02

    Applicant: Texas Instruments Incorporated

    Inventor： Jaiganesh Balakrishnan ,  Sarma Sundareswara Gunturi ,  Pankaj Gupta ,  Indu Prathapan

    IPC: H04L27/26

    CPC classification number: H04L27/2624

    Abstract: The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.

    Methods and systems for generation of balanced secondary clocks from root clock
    7.
    发明授权
    Methods and systems for generation of balanced secondary clocks from root clock 有权

    公开(公告)号：US11422586B1

    公开(公告)日：2022-08-23

    申请号：US17488559

    申请日：2021-09-29

    Applicant: Texas Instruments Incorporated

    Inventor： Aswath Vs ,  Sundarrajan Rangachari ,  Sarma Sundareswara Gunturi ,  Sanjay Pennam

    IPC: G06F1/08 ,  G06F1/10

    Abstract: A system for generating secondary clock signals from a primary clock signal includes a dithered clock divider which has a first input adapted to receive the primary clock signal and a second input adapted to receive a random division ratio. The dithered clock divider provides a dithered clock signal. The system includes a multi-phase clock generator which has a first input adapted to receive the primary clock signal, a second input adapted to receive the dithered clock signal, and a third input adapted to receive a pseudo-random pattern. The multi-phase clock generator provides the secondary clock signals from multiple phases of the dithered clock signal. The system includes a pseudo-random pattern generator which provides the pseudo-random pattern.

    DIGITAL CLOCK GENERATION WITH RANDOMIZED DIVISION OF A SOURCE CLOCK
    8.
    发明申请
    DIGITAL CLOCK GENERATION WITH RANDOMIZED DIVISION OF A SOURCE CLOCK 审中-公开

    公开(公告)号：US20200153444A1

    公开(公告)日：2020-05-14

    申请号：US16680046

    申请日：2019-11-11

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sarma Sundareswara Gunturi ,  Jawaharlal Tangudu ,  Sundarrajan Rangachari

    IPC: H03L7/18 ,  H03K3/84 ,  H04B1/40

    Abstract: A digital clock generator for a digital clock domain interfaced to another clock domain through a FIFO, includes division selector circuitry to provide an input randomizing sequence of clock division factors, selected from a defined set of clock division factors corresponding to a target average clock division, and division arbitration circuitry to generate a drift-corrected randomizing sequence of clock division factors, based at least in part on the input randomizing sequence of clock division factors, and an accumulated drift correction signal. A clock drift control loop generates the accumulated drift correction signal, based at least in part on an accumulated clock drift relative to the target average clock division. Clock generation can be based on randomized division with the drift-corrected randomizing sequence of clock division factors. The drift-corrected randomizing sequence of clock division factors can be generated so that clock drift is bounded based on a FIFO depth.

    Peak-to-average power reduction using guard tone filtering
    10.
    发明授权
    Peak-to-average power reduction using guard tone filtering 有权

    公开(公告)号：US09967123B1

    公开(公告)日：2018-05-08

    申请号：US15426464

    申请日：2017-02-07

    Applicant: Texas Instruments Incorporated

    Inventor： Jaiganesh Balakrishnan ,  Sarma Sundareswara Gunturi ,  Pankaj Gupta ,  Indu Prathapan

    IPC: H04L27/00 ,  H04L27/26

    CPC classification number: H04L27/2615 ,  H04L27/2634

    Abstract: The disclosure provides a circuit. The circuit includes an IFFT (inverse fast fourier transform) block. The IFFT block generates a modulated signal in response to a data signal. A clip logic block is coupled to the IFFT block, and generates a clipped signal in response to the modulated signal. A first subtractor is coupled to the clip logic block and the IFFT block, and subtracts the modulated signal from the clipped signal to generate an error signal. A cyclic filter is coupled to the first subtractor, and filters the error signal to generate a filtered error signal. A second subtractor is coupled to the cyclic filter and the IFFT block. The second subtractor subtracts the filtered error signal from the modulated signal to generate a processed signal.

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