公开(公告)号：US20250088148A1

公开(公告)日：2025-03-13

申请号：US18399974

申请日：2023-12-29

Applicant: Texas Instruments Incorporated

Inventor： Ajay Kumar REDDY ,  Arpan THAKKAR ,  Peeyoosh MIRAJKAR ,  Bichoy BAHR

IPC: H03B5/36 ,  H03K5/00

Abstract: A circuit includes a resonator, a transistor pair, and a common-mode feedback circuit. The transistor pair is cross-coupled across the resonator. The common-mode feedback circuit is coupled to the transistor pair. The common-mode feedback circuit includes first and second degeneration cells. The second degeneration cell is connected in parallel with the first degeneration cell. The second degeneration cell is configured to switchably vary a current flow through the transistor pair.

公开(公告)号：US20240113716A1

公开(公告)日：2024-04-04

申请号：US17956576

申请日：2022-09-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yogesh DARWHEKAR ,  Abhrarup BARMAN ROY ,  Subhashish MUKHERJEE ,  Peeyoosh MIRAJKAR

IPC: H03K21/08 ,  H03K17/687

CPC classification number: H03K21/08 ,  H03K17/6871

Abstract: In an example, a system includes an N divider coupled to an output of a low dropout regulator. The system also includes a load balancing circuit coupled to the N divider and configured to sink a load balancing current at the output of the low dropout regulator during one or more phases of the N divider. The system includes a switch coupled to the load balancing circuit and configured to connect the load balancing circuit to the output of the low dropout regulator during the one or more phases of the N divider.

公开(公告)号：US20220382320A1

公开(公告)日：2022-12-01

申请号：US17683185

申请日：2022-02-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Apoorva BHATIA ,  Pranav KUMAR ,  Abhrarup BARMAN ROY ,  Peeyoosh MIRAJKAR ,  Raghavendra REDDY

IPC: G06F1/12 ,  H03K19/20 ,  H03K3/037 ,  G06F1/08

Abstract: In an example, a system is adapted to be coupled to a load device having a load clock. The system includes a clock generation device with a pin. The system also includes a capture circuit coupled to the pin and operable to sample a value at the pin. The system includes a D flip-flop having a data input coupled to the capture circuit, a clock input coupled to a clock, and having an output, where the D flip-flop is operable to provide, at the output, a system reference event (SYSREF) signal to align the load clock to the clock, based at least in part on the value at the pin.