公开(公告)号：US20210119661A1

公开(公告)日：2021-04-22

申请号：US17072104

申请日：2020-10-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriram MURALI ,  Jaiganesh BALAKRISHNAN ,  Pooja SUNDAR ,  Harshavardhan ADEPU ,  Wenjing LU ,  Yeswanth GUNTUPALLI

IPC: H04B1/40 ,  H04B1/00

Abstract: A digital up-converter (DUC) includes conjugate-mixer-combiner. The conjugate-mixer-combiner includes a pre-combiner configured to generate combinations of a first in-phase (I) value to be transmitted at a first frequency of a first frequency band, a first quadrature (Q) value to be transmitted at the first frequency of a first frequency band, a second I value for to be transmitted at a second frequency of a second frequency band, and a second Q value to be transmitted at the second frequency of a second frequency band. The conjugate-mixer-combiner further includes a plurality of multipliers collectively configured to shift the combinations based on an average difference between the first frequency and the second frequency.

公开(公告)号：US20220029657A1

公开(公告)日：2022-01-27

申请号：US17493943

申请日：2021-10-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriram MURALI ,  Jaiganesh BALAKRISHNAN ,  Pooja SUNDAR ,  Harshavardhan ADEPU ,  Wenjing LU ,  Yeswanth GUNTUPALLI

IPC: H04B1/40 ,  H04B1/00

Abstract: A digital up-converter (DUC) includes conjugate-mixer-combiner. The conjugate-mixer-combiner includes a pre-combiner configured to generate combinations of a first in-phase (I) value to be transmitted at a first frequency of a first frequency band, a first quadrature (Q) value to be transmitted at the first frequency of a first frequency band, a second I value for to be transmitted at a second frequency of a second frequency band, and a second Q value to be transmitted at the second frequency of a second frequency band. The conjugate-mixer-combiner further includes a plurality of multipliers collectively configured to shift the combinations based on an average difference between the first frequency and the second frequency.

公开(公告)号：US20220116030A1

公开(公告)日：2022-04-14

申请号：US17558794

申请日：2021-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriram MURALI ,  Jaiganesh BALAKRISHNAN ,  Ram Narayan KRISHNA NAMA MONY ,  Pooja SUNDAR

IPC: H03K5/1252 ,  G11C19/28 ,  G06F1/10 ,  G06F1/08 ,  H03K19/21

Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.

公开(公告)号：US20170322773A1

公开(公告)日：2017-11-09

申请号：US15587096

申请日：2017-05-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal TANGUDU ,  Suvam NANDI ,  Pooja SUNDAR ,  Jaiganesh BALAKRISHNAN

IPC: G06F7/523 ,  H03D7/16 ,  G06F7/50

CPC classification number: G06F7/523 ,  G06F7/50 ,  H03D7/161

Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.

公开(公告)号：US20210119622A1

公开(公告)日：2021-04-22

申请号：US17071302

申请日：2020-10-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriram MURALI ,  Jaiganesh BALAKRISHNAN ,  Ram Narayan KRISHNA NAMA MONY ,  Pooja SUNDAR

IPC: H03K5/1252 ,  G06F1/10 ,  G11C19/28 ,  H03K19/21 ,  G06F1/08 ,  H03K5/00

Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.