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公开(公告)号：US20180241413A1
公开(公告)日：2018-08-23
申请号：US15960591
申请日：2018-04-24
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jawaharlal TANGUDU , Suvam NANDI , Jaiganesh BALAKRISHNAN
Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.
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公开(公告)号：US20210391944A1
公开(公告)日：2021-12-16
申请号：US17462055
申请日：2021-08-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sanjay PENNAM , Vamsi Krishna KANDALLA , Brahmendra Reddy YATHAM , Shailesh WARDHEN , Jaiganesh BALAKRISHNAN , Jawaharlal TANGUDU
Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.
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公开(公告)号：US20170324423A1
公开(公告)日：2017-11-09
申请号：US15392491
申请日：2016-12-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jawaharlal TANGUDU , Suvam NANDI , Jaiganesh BALAKRISHNAN
CPC classification number: H03M7/6047 , H03D7/165 , H03D2200/0056 , H03H17/0664 , H03M7/3059
Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.
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公开(公告)号：US20210176005A1
公开(公告)日：2021-06-10
申请号：US16936065
申请日：2020-07-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sanjay PENNAM , Vamsi Krishna KANDALLA , Brahmendra Reddy YATHAM , Shailesh WARDHEN , Jaiganesh BALAKRISHNAN , Jawaharlal TANGUDU
Abstract: A transmitter includes a data stream encoder layer having an output and a pattern generator having a bit pattern output. The transmitter further includes a first multiplexer having first and second inputs and a first multiplexer output. The first input is coupled to the output of the data stream encoder layer, and the second input is coupled to the bit pattern output of the pattern generator. While at least a portion of the data stream encoder layer is powered down, the pattern generator is configured to provide bit patterns on its bit pattern output, a control signal to the first multiplexer is configured to select the second input of the first multiplexer, and the first multiplexer is configured to output the bit patterns on the output of the first multiplexer.
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公开(公告)号：US20200322067A1
公开(公告)日：2020-10-08
申请号：US16907051
申请日：2020-06-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sarma Sundareswara GUNTURI , Chandrasekhar SRIRAM , Jawaharlal TANGUDU , Sashidharan VENKATRAMAN
Abstract: A channel response generating module and method for generating a channel response based on a ratio of a channel response corresponding to an image signal frequency bin in relation to a channel response corresponding to a traffic signal frequency bin, or a channel response corresponding to a first frequency bin in relation to a channel response corresponding to a second frequency bin, and a zero-IF signal transmitter employing the channel response generating module and method to efficiently suppress image signals or compensate traffic signals during transmission of IQ RF signals.
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Patent Agency Ranking
公开(公告)号：US20170063575A1
公开(公告)日：2017-03-02
申请号：US15246248
申请日：2016-08-24
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jaiganesh BALAKRISHNAN , Jawaharlal TANGUDU , Sreenath Potty NARAYANAN
IPC: H04L25/03 , H04L12/26 , H04L12/741
CPC classification number: H04L25/03006 , H04L43/022 , H04L45/745
Abstract: A re-sampler comprises: a plurality of multipliers configured to receive an input sample; and a plurality of accumulators coupled to the multipliers and configured to form multiplier-accumulator (MAC) units with the multipliers, wherein the MAC units are configured to: compute partial products from the input sample, accumulate the partial products over clock cycles, and sequentially generate output samples based on the computing and the accumulating. A method comprises: receiving input samples; computing partial products from the input samples; accumulating the partial products over clock cycles; and sequentially generating output samples based on the computing and the accumulating.
Abstract translation: 重新取样器包括：多个乘法器，被配置为接收输入样本; 以及多个累加器，其耦合到所述乘法器并且被配置为与所述乘法器形成乘法器累加器（MAC）单元，其中所述MAC单元被配置为：从所述输入样本计算部分乘积，在时钟周期内累积所述部分乘积， 基于计算和累积生成输出样本。 一种方法包括：接收输入样本; 从输入样本计算部分产品; 在时钟周期内积累部分产品; 并基于计算和累加顺序产生输出样本。
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公开(公告)号：US20220190856A1
公开(公告)日：2022-06-16
申请号：US17689627
申请日：2022-03-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sarma Sundareswara GUNTURI , Jagannathan VENKATARAMAN , Jawaharlal TANGUDU , Narasimhan RAJAGOPAL , Eeshan MIGLANI
Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.
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公开(公告)号：US20210175914A1
公开(公告)日：2021-06-10
申请号：US17112137
申请日：2020-12-04
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sarma Sundareswara GUNTURI , Jagannathan VENKATARAMAN , Jawaharlal TANGUDU , Narasimhan RAJAGOPAL , Eeshan MIGLANI
Abstract: Techniques maintaining receiver reliability, including determining a present attenuation level for an attenuator, wherein the attenuation level is set by a gain controller, determining a relative reliability threshold based on the present attenuation level, receiving a radio frequency (RF) signal, determining a voltage level of the received RF signal, comparing the voltage level of the received RF signal to the relative reliability threshold to determine that a reliability condition exists, and overriding, in response to the determination that the reliability condition exists, the present attenuation level set by the gain controller with an override attenuation level based on the present attenuation level.
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公开(公告)号：US20210105021A1
公开(公告)日：2021-04-08
申请号：US17061730
申请日：2020-10-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jawaharlal TANGUDU , Pankaj GUPTA , Sreenath Narayanan POTTY , Ajai PAULOSE , Chandrasekhar SRIRAM , Mahesh Ravi VARMA , Shabbar Abbasi VEJLANI , Neeraj SHRIVASTAVA , Himanshu VARSHNEY , Divyeshkumar Mahendrabhai PATEL , Raju Kharataram CHAUDHARI
Abstract: A non-linearity correction circuit includes a non-linearity coefficient estimation circuit. The non-linearity coefficient estimation circuit includes a data capture circuit, a non-linearity term generation circuit, a time-to-frequency conversion circuit, a bin identification circuit, a residual non-linearity conversion circuit, and a non-linearity coefficient generation circuit. The non-linearity term generation circuit is coupled to the data capture circuit. The time-to-frequency conversion circuit is coupled to the data capture circuit and the non-linearity term generation circuit. The bin identification circuit is coupled to the time-to-frequency conversion circuit. The residual non-linearity conversion circuit is coupled to the bin identification circuit. The non-linearity coefficient generation circuit is coupled to the bin identification circuit and the residual non-linearity conversion circuit.
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公开(公告)号：US20210075368A1
公开(公告)日：2021-03-11
申请号：US16953666
申请日：2020-11-20
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: A phase coherent NCO circuit includes a base frequency NCO, a phase seeding circuit, a scaled frequency NCO, a sine/cosine generator. The base frequency NCO is configured to generate base phase values based on a base frequency control word. The phase seeding circuit is coupled to the base frequency NCO. The phase seeding circuit is configured to generate a seed phase value based on the base phase values and a scale factor value. The scaled frequency NCO is coupled to the phase seeding circuit. The scaled frequency NCO is configured to generate oscillator phase values based on the phase seed value and an oscillator frequency control word. The sine/cosine generator is coupled to the scaled frequency NCO. The sine/cosine generator is configured to generate oscillator output samples based on the oscillator phase values.
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