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    ADAPTIVE BLANKING TIMER FOR SHORT CIRCUIT DETECTION
    1.
    发明申请
    ADAPTIVE BLANKING TIMER FOR SHORT CIRCUIT DETECTION 有权
    用于短路电路检测的自适应保护定时器

    公开(公告)号：US20150372678A1

    公开(公告)日：2015-12-24

    申请号：US14742540

    申请日：2015-06-17

    Applicant: Texas Instruments Incorporated

    Inventor： Ruochen Zhang ,  Xiaofan Qiu ,  Jingwei Xu ,  Qingjie Ma

    IPC: H03K19/0175

    CPC classification number: H03K17/165 ,  H03K17/0822 ,  H03K17/284 ,  H03K19/017509 ,  H03K2217/0027

    Abstract: A gate driver IC for driving an NMOS transistor having a drain coupled through a load to a power supply. A gate driver output drives the gate of the NMOS transistor. A comparator receives the drain voltage of the NMOS transistor and compares it to a reference voltage representative of a short circuit condition between the drain and the power supply. The comparator outputs a first value if the drain voltage is greater than the reference voltage and outputs a second value if the drain voltage is less than or equal to the reference voltage. Control circuitry receives the output of the first comparator and pulls the voltage of the gate driver output low if the comparator output is of the first value. Adaptive masking circuitry is operable, upon an application of an “on” signal to the gate driver output, to mask the output of the comparator such that a condition of the drain voltage being greater than the reference voltage does not cause the control circuitry to pull the voltage of the gate driver output low. The adaptive masking circuitry detects a Miller plateau in the gate voltage of the external NMOS transistor. The adaptive masking circuitry stops masking the output of the comparator after the end of the Miller plateau.

    Abstract translation: 一种用于驱动具有通过负载耦合到电源的漏极的NMOS晶体管的栅极驱动器IC。 栅极驱动器输出驱动NMOS晶体管的栅极。 比较器接收NMOS晶体管的漏极电压，并将其与表示漏极和电源之间的短路状态的参考电压进行比较。 如果漏极电压大于参考电压，则比较器输出第一值，并且如果漏极电压小于等于参考电压则输出第二值。 如果比较器输出为第一值，则控制电路接收第一比较器的输出并将栅极驱动器的电压拉低。 自适应屏蔽电路在对栅极驱动器输出施加“导通”信号时可操作以掩蔽比较器的输出，使得漏极电压大于参考电压的条件不会导致控制电路拉 栅极驱动器的电压输出低电平。 自适应屏蔽电路检测外部NMOS晶体管的栅极电压的米勒平台。 自适应屏蔽电路在米勒平台结束后停止屏蔽比较器的输出。

    Adaptive thermal overshoot and current limiting protection for MOSFETs
    2.
    发明授权
    Adaptive thermal overshoot and current limiting protection for MOSFETs 有权

    公开(公告)号：US11367719B2

    公开(公告)日：2022-06-21

    申请号：US17122682

    申请日：2020-12-15

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Qingjie Ma ,  Wei Xu ,  Jingwei Xu ,  Yang Wang

    IPC: H01L27/02 ,  H03K17/0812 ,  H03K17/081 ,  H03K17/08

    Abstract: In a described example, an apparatus includes: a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal; an enable terminal coupled to the first gate terminal for receiving an enable signal; a first current mirror coupled between the first input terminal and a first terminal of a first series resistor and having an input coupled to the first gate terminal; and a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first series resistor, the first series resistor having a second terminal coupled to the output terminal.

    Adaptive thermal overshoot and current limiting protection for MOSFETs
    3.
    发明授权
    Adaptive thermal overshoot and current limiting protection for MOSFETs 有权

    公开(公告)号：US10896905B2

    公开(公告)日：2021-01-19

    申请号：US16751491

    申请日：2020-01-24

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Qingjie Ma ,  Wei Xu ,  Jingwei Xu ,  Yang Wang

    IPC: H03K17/0812 ,  H01L27/02 ,  H03K17/081 ,  H03K17/08

    Abstract: In a described example, an apparatus includes: a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal; an enable terminal coupled to the first gate terminal for receiving an enable signal; a first current mirror coupled between the first input terminal and a first terminal of a first series resistor and having an input coupled to the first gate terminal; and a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first series resistor, the first series resistor having a second terminal coupled to the output terminal.

    Adaptive blanking timer for short circuit detection
    4.
    发明授权
    Adaptive blanking timer for short circuit detection 有权
    用于短路检测的自适应消隐定时器

    公开(公告)号：US09520879B2

    公开(公告)日：2016-12-13

    申请号：US14742540

    申请日：2015-06-17

    Applicant: Texas Instruments Incorporated

    Inventor： Ruochen Zhang ,  Xiaofan Qiu ,  Jingwei Xu ,  Qingjie Ma

    IPC: H03B1/00 ,  H03K19/0175

    CPC classification number: H03K17/165 ,  H03K17/0822 ,  H03K17/284 ,  H03K19/017509 ,  H03K2217/0027

    Abstract: A gate driver IC for driving an NMOS transistor having a drain coupled through a load to a power supply. A gate driver output drives the gate of the NMOS transistor. A comparator receives the drain voltage of the NMOS transistor and compares it to a reference voltage representative of a short circuit condition between the drain and the power supply. The comparator outputs a first value if the drain voltage is greater than the reference voltage and outputs a second value if the drain voltage is less than or equal to the reference voltage. Control circuitry receives the output of the first comparator and pulls the voltage of the gate driver output low if the comparator output is of the first value. Adaptive masking circuitry is operable, upon an application of an “on” signal to the gate driver output, to mask the output of the comparator such that a condition of the drain voltage being greater than the reference voltage does not cause the control circuitry to pull the voltage of the gate driver output low. The adaptive masking circuitry detects a Miller plateau in the gate voltage of the external NMOS transistor. The adaptive masking circuitry stops masking the output of the comparator after the end of the Miller plateau.

    Abstract translation: 一种用于驱动具有通过负载耦合到电源的漏极的NMOS晶体管的栅极驱动器IC。 栅极驱动器输出驱动NMOS晶体管的栅极。 比较器接收NMOS晶体管的漏极电压，并将其与表示漏极和电源之间的短路状态的参考电压进行比较。 如果漏极电压大于参考电压，则比较器输出第一值，并且如果漏极电压小于等于参考电压则输出第二值。 如果比较器输出为第一值，则控制电路接收第一比较器的输出并将栅极驱动器的电压拉低。 自适应屏蔽电路在对栅极驱动器输出施加“导通”信号时可操作以掩蔽比较器的输出，使得漏极电压大于参考电压的条件不会导致控制电路拉 栅极驱动器的电压输出低电平。 自适应屏蔽电路检测外部NMOS晶体管的栅极电压的米勒平台。 自适应屏蔽电路在米勒平台结束后停止屏蔽比较器的输出。

    ADAPTIVE THERMAL OVERSHOOT AND CURRENT LIMITING PROTECTION FOR MOSFETS
    5.
    发明申请
    ADAPTIVE THERMAL OVERSHOOT AND CURRENT LIMITING PROTECTION FOR MOSFETS 有权

    公开(公告)号：US20210104515A1

    公开(公告)日：2021-04-08

    申请号：US17122682

    申请日：2020-12-15

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Qingjie Ma ,  Wei Xu ,  Jingwei Xu ,  Yang Wang

    IPC: H01L27/02 ,  H03K17/0812 ,  H03K17/081

    Abstract: In a described example, an apparatus includes: a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal; an enable terminal coupled to the first gate terminal for receiving an enable signal; a first current mirror coupled between the first input terminal and a first terminal of a first series resistor and having an input coupled to the first gate terminal; and a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first series resistor, the first series resistor having a second terminal coupled to the output terminal.

    High Speed FlexLED Digital Interface
    6.
    发明申请
    High Speed FlexLED Digital Interface 审中-公开

    公开(公告)号：US20200042032A1

    公开(公告)日：2020-02-06

    申请号：US16218664

    申请日：2018-12-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ruochen Zhang ,  Wei Xu ,  Hongyan Wu ,  Qingjie Ma

    IPC: G06F1/08 ,  H04B7/26 ,  H03L7/07 ,  H04J3/06

    Abstract: A system for a network of one or more off-board subsystems is provided for controlling automobile subsystems such as vehicle lighting. Such a system may be compatible with a universal asynchronous receiver transmitter (UART) interface and it may address timing issues by using a protocol having a synchronization frame (sync frame) such that a clock signal may be recovered from the sync frame sent by an off-board master device 202, such as a microcontroller unit 208, to a satellite/slave 211 device. Such a protocol permits elimination of a crystal clock oscillator and phase-locked loop located at satellite, thereby dispensing with an otherwise significant cost.

    ADAPTIVE BLANKING TIMER FOR SHORT CIRCUIT DETECTION
    7.
    发明申请
    ADAPTIVE BLANKING TIMER FOR SHORT CIRCUIT DETECTION 审中-公开
    用于短路电路检测的自适应保护定时器

    公开(公告)号：US20170070222A1

    公开(公告)日：2017-03-09

    申请号：US15347380

    申请日：2016-11-09

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Ruochen Zhang ,  Xiaofan Qiu ,  Jingwei Xu ,  Qingjie Ma

    IPC: H03K17/16

    CPC classification number: H03K17/165 ,  H03K17/0822 ,  H03K17/284 ,  H03K19/017509 ,  H03K2217/0027

    Abstract: A gate driver IC for driving an NMOS transistor having a drain coupled through a load to a power supply. A gate driver output drives the gate of the NMOS transistor. A comparator receives the drain voltage of the NMOS transistor and compares it to a reference voltage representative of a short circuit condition between the drain and the power supply. The comparator outputs a first value if the drain voltage is greater than the reference voltage and outputs a second value if the drain voltage is less than or equal to the reference voltage. Control circuitry receives the output of the first comparator and pulls the voltage of the gate driver output low if the comparator output is of the first value. Adaptive masking circuitry is operable, upon an application of an “on” signal to the gate driver output, to mask the output of the comparator such that a condition of the drain voltage being greater than the reference voltage does not cause the control circuitry to pull the voltage of the gate driver output low. The adaptive masking circuitry detects a Miller plateau in the gate voltage of the external NMOS transistor. The adaptive masking circuitry stops masking the output of the comparator after the end of the Miller plateau.

    Abstract translation: 一种用于驱动具有通过负载耦合到电源的漏极的NMOS晶体管的栅极驱动器IC。 栅极驱动器输出驱动NMOS晶体管的栅极。 比较器接收NMOS晶体管的漏极电压，并将其与表示漏极和电源之间的短路状态的参考电压进行比较。 如果漏极电压大于参考电压，则比较器输出第一值，并且如果漏极电压小于等于参考电压则输出第二值。 如果比较器输出为第一值，则控制电路接收第一比较器的输出并将栅极驱动器的电压拉低。 自适应屏蔽电路在对栅极驱动器输出施加“导通”信号时可操作以掩蔽比较器的输出，使得漏极电压大于参考电压的条件不会导致控制电路拉 栅极驱动器的电压输出低电平。 自适应屏蔽电路检测外部NMOS晶体管的栅极电压的米勒平台。 自适应屏蔽电路在米勒平台结束后停止屏蔽比较器的输出。

    Adaptive thermal overshoot and current limiting protection for MOSFETs
    10.
    发明授权
    Adaptive thermal overshoot and current limiting protection for MOSFETs 有权

    公开(公告)号：US10586791B2

    公开(公告)日：2020-03-10

    申请号：US16035007

    申请日：2018-07-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Qingjie Ma ,  Wei Xu ,  Jingwei Xu ,  Yang Wang

    IPC: H03K17/0812 ,  H01L27/02 ,  H03K17/081 ,  H03K17/08

    Abstract: In a described example, an apparatus includes: a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal; an enable terminal coupled to the first gate terminal for receiving an enable signal; a first current mirror coupled between the first input terminal and a first terminal of a first series resistor and having an input coupled to the first gate terminal; and a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first series resistor, the first series resistor having a second terminal coupled to the output terminal.

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