公开(公告)号：US10763889B1

公开(公告)日：2020-09-01

申请号：US16661456

申请日：2019-10-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Uttam Kumar Agarwal ,  Anand Kannan ,  Ramamurthy Vishweshwara ,  Anand Subramanian ,  Pedro Ramon Gelabert ,  Diljith Mathal Thodi ,  Abhijit Anant Patki

IPC: H03M3/00 ,  H03G3/00 ,  H03G1/00 ,  H03G3/30 ,  H03M7/34 ,  H03M1/12 ,  H03M1/06 ,  H03G5/02

Abstract: A circuit includes a programmable gain amplifier (PGA) having a PGA output. The circuit further includes a delta-sigma modulator having an input coupled to the PGA output. The circuit also includes a digital filter and a dynamic range enhancer (DRE) circuit. The digital filter is coupled to the delta-sigma modulator output. The DRE circuit is coupled to the delta-sigma modulator output and to the PGA. The DRE circuit is configured to monitor a signal level of the delta-sigma modulator output. Responsive to the signal level being less than a DRE threshold, the DRE circuit is configured to program the PGA for a gain level greater than unity gain and to cause the digital filter to implement an attenuation of a same magnitude as the gain level to be programmed into the PGA.

公开(公告)号：US10812098B1

公开(公告)日：2020-10-20

申请号：US16454335

申请日：2019-06-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ramamurthy Vishweshwara ,  Pramod Kumar Baskar

IPC: H03M1/34 ,  H03M1/46 ,  H03M1/12 ,  H03M1/66 ,  H03M1/36 ,  G05F3/02

Abstract: An analog-to-digital converter (ADC) includes a capacitive digital-to-analog converter (CDAC), a comparator, and a successive approximation register (SAR) control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an output of the comparator and to an input of the CDAC. The SAR control circuit includes a flip-flop. The flip-flop includes a clock input terminal, a data input terminal, and an output. The clock input terminal is coupled to the output of the comparator. The data input terminal coupled to a constant voltage source. The flip-flop can include an enable input terminal coupled to a SAR state circuit. The output is coupled to the CDAC.